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HMS81C43XX / GMS87C4060
HMS81C43XX/GMS87C4060
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
1. OVERVIEW
1.1 Description
The HMS81C43XX/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 8~32K(60K) bytes of ROM. The device is one of GMS800 family. The HYNIX's HMS81C43XX/GMS87C4060 is a powerful microcontroller which provides a highly flexible and cost effective solution to many TV applications. The HMS81C43XX/GMS87C4060 provides the following standard features: 8~32K(60K) bytes of ROM, 256~512/1,536 bytes of RAM, 8-bit timer/counter .
Device name ROM Size 8~32K bytes Mask ROM 60K bytes EPROM RAM Size 256~512 bytes 1,536 bytes Package 32 PDIP 52 SDIP
HMS81C43XX
GMS87C4060
1.2 GMS87C4060 (OTP) Features
* 60K Bytes On-chip Program Memory * 1,536 Bytes of On-chip Data RAM (Included 256 bytes stack memory) * Instruction Cycle Time (ex:NOP) - 0.5us at 8MHz * 40 Programmable I/O pins - 33 Input/Ooutput and 7 Output pins * Serial I/O : 8bit x 1ch * I2C Bus interface - Multimaster (2 Pairs interface pins) * A/D Converter : 8bit x 6ch (TBD LSB) * Pulse Width Modulation - 14bit x 1ch - 8bit x 6ch * Timer - Timer/Counter : 8bit x 4ch (16bit x 2ch) - Basic interval timer : 8bit x 1ch - Watch Dog Timer * Number of Interrupt sources : 18 * On Screen Display - Number of characters : 512 (6 characters are reserved for IC test) - Character size : 12 dots(X) x 16 dots(Y) - Character display size : Large, Medium, Small - DIsplay capability : 24Characters x 16 Lines - Character, Back ground color : 16kinds - Special functions : Rounding, Outline, Sprite, Shadow, Half Tone Background,... * Buzzer Driving port - 500Hz ~ 250kHz @8MHz (Duty 50%) * Operating Range : 4.5V to 5.5V
1.3 HMS81C43XX Family Features
* On-chip Program Memry and Data memry HMS81C4332 ( 32K ROM, 512 RAM) HMS81C4324 ( 24K ROM, 256 RAM) HMS81C4316 ( 16K ROM, 256 RAM) HMS81C4308 ( 8K ROM, 256 RAM) (Included 64/256 bytes stack memory) * Instruction Cycle Time (ex:NOP) - 1.0us at 4MHz * 21 Programmable I/O pins - 19 Input/Output and 3 Output pins * I2C Bus interface - Multimaster (2 Pairs interface pins)
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* A/D Converter : 8bit x 6ch (TBD LSB) * Pulse Width Modulation - 14bit x 1ch - 8bit x 2ch * Timer - Timer/Counter : 8bit x 4ch (16bit x 2ch) - Basic interval timer : 8bit x 1ch - Watch Dog Timer * Number of Interrupt sources : 18 * On Screen Display - Number of characters : 256
- Character size : 12 dots(X) x 16 dots(Y) - Character display size : Large, Medium, Small - DIsplay capability : 24Characters x 16 Lines - Character, Back ground color : 8 kinds - Special functions : Rounding, Outline, Shadow, Half tone Background... * Buzzer Driving port - 250Hz ~ 125kHz @4MHz (Duty 50%) * Operating Range : 4.5V to 5.5V *
1.4 Development Tools
The HMS81C43XX/GMS87C4060 is supported by a fullfeatured macro assembler / linker , OSD font editor, an incircuit emulator CHOICE-DrTM.
In Circuit Emulators CHOICE-Dr. (with EVA81C4xxx board) Assembler / Linker Font Editor Debugger HYNIX's Macro Assembler / Linker MS-Windows GUI version MS-Windows GUI version
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2. BLOCK DIAGRAM
R,G,B
R10 / AN0 R11 / AN1 R12 / AN2 R13 / AN3 R14 / AN4 R15 / AN5 R16 / VD R17 / HD
R50 / BUZZ R51 / PWM8 R54 / YM R52 / INT0 R55 / YS R53 R56 / I
OSC1 OSC2
OSD (On Screen Display) Controller
OSD Display Memory D a ta b u s
R1
R5
Data Memory Program Memory Vector Table RESET TEST
Stack pointer
PSW
ALU
Accumulator & Index X,Y
8bit A/D C onvertor
Buzzer
PC Interrupt Controller
PWM 14bit x 1 8bit x 6
System controller System Clock Controller Timing generator
8-bit Basic Interval Tim er Watchdog Timer 8-bit x 4 Timer/ Counter Interrupt Interval M easure Serial I/O Interface I2C Interface
XIN XOUT
Clock generator D a ta b u s
VDD VSS
Power Supply
R0
R6
R2
R4
R00 R01 R02 R03 R04 R05 R06 R07
R67 / INT1
R20 / INT2 R21 / Sclk R22 / Sout R23 / Sin R24 / INT3 R25 / EC2 R26 / INT4 R27 / EC3
R40 R41 R42 R43
/ PWM0 / PWM1 / PWM2 / PWM3
R44 / SCL0 R45 / SCL1 / PWM4 R46 / SDA0 R47 / SDA1 / PWM5
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3. PIN ASSIGNMENT
R17/HD R16/VD R15/AN5 R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0 Vss Xin Xout R47/SDA1/PWM5 R46/SDA0 R45/SCL1/PWM4 R44/SCL0 R27/EC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
R G B R56 R55/YS R54/YM OSC1 OSC2 TEST Vdd RESET R53 R52/INT0 R51/PWM8 R50/BUZZ R26/INT4
HYNIX HMS81C4332
R27/EC3 R26/INT4 R25/EC2 R24/INT3 R23/Sin R22/Sout R21/Sclk R20/INT2 R17/HD R16/VD RESET Vss Xout Xin R15/AN5 R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0 R07 R06 R05 R04 R03 R67/INT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
R40/PWM0 R41/PWM1 R42/PWM2 R43/PWM3 R44/SCL0 R45/SCL1/PWM4 R46/SDA0 R47/SDA1/PWM5 R50/BUZZ R51/PWM8 R52/INT0 R53 Vss Vdd TEST OSC1 OSC2 R54/YM R55/YS R56/I B G R R00 R01 R02
HYNIX GMS87C4060
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4. PACKAGE DIAGRAM
UNIT: inch
HYNIX HMS81C4332
TYP 0.600 BSC 1.665 1.645 0.2 max 0.550 0.530
MIN 0.015 0.140 0.120 0.022 0.015 0 ~ 15
2 0.01 8 0.00
0.065 0.045
0.1 BSC
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Figure 4-1 52pin Shrink DIP Package Diagram
52
27
0 ~ 15
15.24
13.97
HYNIX GMS87C4060
1 26
0.25
0.25 0.25 0.05
45.97
0.13
3.81
4.38 Max.
0.76
0.13
0.13 0.50 Min.
UNIT: mm
3.24 0.47 0.13 1.02 0.25 1.778 0.25
0.20
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should not be connected . RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. OSC1: Input to the internal On Screen Display operating circuit. OSC2: Output from the inverting OSC1 amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various following special features.
Port pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate function AN0 (A/D converter input 0) AN1 (A/D converter input 1) AN2 (A/D converter input 2) AN3 (A/D converter input 3) AN4 (A/D converter input 4) AN5 (A/D converter input 5) VD (Vertical Sync. input) HD (Horisontal Sync. input)
R40~R47: R40~R43 are 8-bit NMOS open drain output and R45~R47 are bidirectional CMOS Input / NMOS open drain output port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R4 serves the functions of the various following special features.
Port pin R40 R41 R42 R43 R44 R45 R46 R47 Alternate function PWM0 (Pulse Width Modulation output 0) PWM1 (Pulse Width Modulation output 1) PWM2 (Pulse Width Modulation output 2) PWM3 (Pulse Width Modulation output 3) SCL0 (I2C Clock 0) SCL1 (I2C Clock 1) PWM4 (Pulse Width Modulation output 4) SDA0 (I2C Data 0) SDA1 (I2C Data 1) PWM5 (Pulse Width Modulation output 5)
R50~R56: R50~R53 are 4-bit CMOS bidirectional I/O and R54~R56 are CMOS output port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features.
Port pin R50 R51 R52 R54 R55 R56 Alternate function BUZZ (Buzzer output) PWM8 (Pulse Width Modulation output 8) INT0 (External interrupt input 0) YM (Back ground) YS (Edge) I (Intencity)
R20~R27: R2 is a 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. In addition, R2 serves the functions of the various following special features.
Port pin R20 R21 R22 R23 R24 R25 R26 R27 Alternate function INT2 (External interrupt input 2) Sclk (Serial communication clock) Sout (Serial communication data out) Sin (Serial communication data in) INT3 (External interrupt input 3) EC2 (Event counter input 2) INT4 (External interrupt input 4) EC3 (Event counter input 3)
R67: R67 is an 1-bit CMOS bidirectional I/O port. R67 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R67 serves the functions of the various following special features.
Port pin R67 Alternate function INT1 (External interrupt input 1)
R,G,B: R,G,B CMOS output port. Each pins controls Red, Green,. Blue color control.
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PIN NAME VDD VSS TEST RESET XIN XOUT OSC1 OSC2 R17/HD R16/VD R G B R56/I R55/YS R54/YM R40/PWM0 R41/PWM1 R42/PWM2 R43/PWM3 R45/SCL1/ PWM4 R47/SDA1/ PWM5 R51/PWM8 R44/SCL0 R46/SDA0 R23/Sin R22/Sout R21/Sclk R27/EC3 R25/EC2 R50/Buzzer
Pin No. 39 12, 40 38 11 14 13 37 36 9 10 30 31 32 33 34 35 52 51 50 49 47 45 43 48 46 5 6 7 1 3 44
In/Out I I I O I O I/O I/O O O O O O O O O O O PWM functions I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Timer event functions Buzzer function Table 5-1 Port Function Description SCI functions I2C functions On screen display functions Supply voltage Circuit ground
Function
For test purposes. Should not be connected. (N.C.) Reset signal input Main oscillation input Main oscillation output On screen display oscillation input On screen display osc. output Horisontal Sync. input Vertical Sync. input Red signal output Green signal output Blue signal output Intencity signal output Edge signal output Background signal output 8bit PWM 8bit PWM 8bit PWM 8bit PWM Include I2C Serial clock 1 (SCL1) Include I2C Serial data 1 (SDA1) 14bit PWM I2C Serial clock 0 I2C Serial data 0 Serial data input Serial data output Serial communication clock Event counter input 3 Event counter input 2 500Hz ~ 250KHz @8MHz
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PIN NAME R52/INT0 R67/INT1 R20/INT2 R24/INT3 R26/INT4 R10/AN0 R11/AN1 R12/AN2 R13/AN3 R14/AN4 R15/AN5 R00 R01 R02 R03 R04 R05 R06 R07 R53
Pin No. 42 26 8 4 2 20 19 18 17 16 15 29 28 27 25 24 23 22 21 41
In/Out I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Table 5-1 Port Function Description Digital I/O functions A/D conversion functions External interrupt functions
Function External interrupt input 0 External interrupt input 1 External interrupt input 2 External interrupt input 3 External interrupt input 4 Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5
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6. PORT STRUCTURES
RESET
VDD
OSC1, OSC2
VDD Main frequency clock
RESET Noise Canceler OSC1 VDD VSS OSC2 VSS
TEST
VSS VDD
OSDON
R00~07, R53
VDD VSS DB Data Reg.
XIN, XOUT
VDD Main frequency clock
DB
Dir. Reg. VSS
Pin
DB RD
MUX
XIN VDD VSS
R10~15 (AN0~5)
XOUT DB VSS VSS DB Dir. Reg. Data Reg.
VDD
Pin
VSS DB RD AN0~5 MUX
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R16, 17, 20, 24, 25, 26, 27, 52, 67
R23/Sin
VDD DB Data Reg. DB Data Reg.
VDD
Selection DB Dir. Reg. VSS DB RD HD,VD, EC2~3 INT0~INT4 RD Sin MUX DB M UX Pin DB Dir. Reg. VSS Pin
R21/Sclk, R22/Sout
R40~43 (PWM0~3)
DB
Data Reg. M UX
DB VDD PWM0~3 Selection Pin
Data Reg. M UX VSS Pin
Sout, Sclk Selection DB Dir. Reg. VSS DB M UX
R44, 45, 46, 47 (SCL, SDA, PWM)
DB RD Sclk SCL,SDA
Data Reg. M UX
PWM4,PWM5 Selection Pin DB Dir. Reg. VSS DB M UX
RD
SCL, SDA
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HMS81C43XX / GMS87C4060
R50/BUZZ, R51/PWM8
DB
Data Reg. M UX
VDD
Buzz, PWM8 Selection Pin DB Dir. Reg. VSS DB M UX
RD
R54/YM, R55/YS, R56/I
VDD OSD ON or Data Reg Write.
DB
Data Reg. M UX
Pin
YM, YS, I Selection VSS
R, G, B
VDD R, G, B
i
Pin
OSD_ON
VSS
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................100 mA Maximum current into VDD pin ............................80 mA Maximum current sunk by (IOL per I/O Pin) ........20 mA Maximum output current sourced by (IOH per I/O Pin) .................................................................................8 mA Maximum current (IOL) ...................................... 80 mA Maximum current (IOH)...................................... 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Symbol Condition Min. Supply Voltage Operating Frequency On Screen Display Operating Frequency Operating Temperature VDD fXIN fOSC TOPR fXIN=8MHz fOSC=16MHz VDD=4.5~5.5V VDD=4.5~5.5V 4.5 4 8 -10 Max. 5.5 8 16 70 V MHz MHz C Unit
7.3 DC Electrical Characteristics - HMS81C43XX
(TA=-10~70C, V DD=4.5~5.5V),
Specifications Parameter Symbol Condition Min. VIH1 VIH2 Low level input voltage VIL1 VIL2 TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 R0, R15~10, R53~50 TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 R0, R15~10, R53~50 IOH = -5mA R0, R1, R2, R5, R67 IOH = -1.2mA R,G,B IOL = 5mA R0, R1, R2, R4, R5, R67, R, G, B VDD 0.8 VDD 0.7 VDD 0 0 VDD - 1 VDD - 1
-
Unit Typ. Max. VDD VDD 0.12 V DD 0.3 VDD 1.0 30 V V V V V V V mA
High level input voltage
High level output voltage
VOH
Low level output voltage Supply current in ACTIVE mode
VOL IDD
-
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Specifications Parameter Symbol Condition Min. pull-up lekage current High input leakage current Low input leakage current Open drain leakage current RAM data retention voltage IRUP VDD = 5.5v, VPIN = 0.4V TEST VDD = 5.5V , VPIN = V DD All input, I/O pins except X IN, OSC1, R47~40 VDD = 5.5V , VPIN = 0V All input, I/O pins except XIN, OSC1, R47~44 VDD = 5.5V , VOH = V DD, N-ch Tr. off R47~40 VDD VDD = 4.5V , VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V SCL0:SCl1 (R44:R45) SDA0:SDA1 (R46:R47) TEST, RESET, Xin, OSC1, R17~16, R27~20, R47~44, R52, R67 -1.5 Typ. Max. -400 A A Unit
IIZH
-5
-
5
IIZL
-5
-
5
A
ILOZ VRAM
1.2
-
10 -
A V
I2C port impedance (I/O Transistor off)
RBS
-
-
120
Hysterisis
Vt+ ~ Vt-
1.0
-
-
V
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7.4 A/D Comparator Characteristics
(TA=-10~70C, V DD=5.0V)
Specifications Parameter Analog Input Voltage Range Accuracy Symbol VAIN NFS AN0~AN5 Pins Min. VSS Typ. Max. VDD V LSB Unit
7.5 AC Characteristics
(TA=-10~70C, V DD=5V10%, VSS=0V)
Specifications Parameter Symbol fXIN fOSC tMCPW tSCPW tMRCP,tMFCP tSRCP,tSFCP tST tIW tRST tECW tREC,tFEC Pins Min. Operating Frequency XIN OSC XIN SCLK XIN SCLK XIN, XOUT INT0~4 RESET EC2, EC3 EC2, EC3 4 8 62.5 0.5 2 8 2 Typ. 20 20 20 20 Max. 8 16 125 MHz MHz nS S nS nS mS tSYS1 tSYS1 tSYS1 nS Unit
External Clock Pulse Width
External Clock Transition Time Oscillation Stabilizing Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width Event Counter Transition Time
1. tSYS is one of 2/fXIN main clock operation mode,
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1/fXIN
tMCPW
tMCPW VDD-0.5V
XIN
tMRCP 1/f SCLK tSCPW tMFCP tSCPW
0.5V
VDD-0.5V
SCLK
tSRCP tSFCP
0.5V
tIW
tIW
INT0 ~ 4
0.8VDD 0.2VDD
tRST
RESET
0.2VDD
tECW
tECW 0.8VDD 0.2VDD
EC2, EC3
tREC
tFEC
Figure 7-1 Timing Chart
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7.6 Typical Characteristics
This data will generate after evaluation. Not available at this time.
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8. MEMORY ORGANIZATION
The GMS81C43xx/GMS87C4060 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 32K/60K bytes of Program memory. Data memory can be read and written to up to 256~512/ 1,536 bytes including the stack area. Font memory has prepared 16K bytes for OSD.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address ( 0100H ~ 013F or 01FFH ) 15 01 8 7 SP 0
(save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 0100H to 01FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used.
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y
Y A
Hardware fixed
Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP for 81C4324 (256 RAM)
LDX TXSP #03FH ; SP 3FH
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU
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after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is addressed by RPR BRK FLAG LSB
N
V
G
B
H
I
Z
C
RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address.
[Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by DPGR register (address 0F8H). It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80 H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RETI instruction
01FC 01FD 01FE 01FF PCL PCH Push down
01FC 01FD 01FE 01FF PSW PCL PCH Push down
01FC 01FD 01FE 01FF PCL PCH Pop up
01FC 01FD 01FE 01FF PSW PCL PCH Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FC 01FD 01FE 01FF A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FC 01FD 01FE 01FF A Pop up 01FFH 0100H Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-4 Stack Operation
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but HMS81C43XX/GMS87C4060 has 8~32K/ 60K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 0FH : : ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B ;1B Y TE INS T RU CT IO N ;IN S TE A D O F 2 B Y TE S ;N O R M A L CA LL
1
;TC A LL A DD R E SS A RE A
87C4060:1000H
81C4332:8000H 81C4324:A000H 81C4316:C000H 81C4308:E000H FEFFH FF00H FFBFH FFC0H FFDFH FFE0H FFFFH PROGRAM MEMORY
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9 H for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Address Vector Area Memory I2C Bus Interface Interrupt Vector Area Serial I/O Interrupt Vector Area Basic Interval Timer Interrupt Vector Area Watchdog Timer Interrupt Vector Area External Interrupt 3/4 Vector Area Timer/Counter 3 Interrupt Vector Area Timer/Counter 1 Interrupt Vector Area V-Sync Interrupt Vector Area 1 Frame Timer Interrupt Vector Area Timer/Counter 2 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 2 Vector Area External Interrupt 1 Vector Area On Screen Display Interrupt Vector Area External Interrupt 0 Vector Area RESET Vector Area
TCALL AREA INTERRUPT VECTOR AREA
PCALL AREA
Figure 8-5 Program Memory Map
0FFE0H E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 8-7 .
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (192 Bytes)
0FFBFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
Upper address is assumed 0FFH. 0D125H Sub-routine
~ ~
Reverse
~ ~
0FF00H 0FF35H Sub-routine
PC: 11111111 11010110 FH FH DH 6 H
0FF00H 0FFD6H 25 D1
A
A
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part in HMS81C4324.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H I2C SERIAL BIT WATCHDOG INT3_4 TIMER3 TIMER1 VSYNC One_Frame TIMER2 TIMER0 INT2 INT1 OSD INT0 RESET 0A000H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; I2C Serial I/O Basic interval timer Watch dog timer Interrupt 3/4 Timer 3 Timer 1 Vertical Sync. 1 Frame interrupt Timer 2 Timer 0 Interrupt 2 Interrupt 1 On Screen Display Interrupt 0 Reset
; Start Address of 24 kbytes Program Memory
;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ; Disable All Interrupts LDX #0 LDA #0 ; RAM Page0 Clear(!0000H->!00BFH) RAM_CLR: STA {X}+ CMPX #0C0H BNE RAM_CLR ; CALL OSD_Stop ; Stop OSD display ; LDX #03FH ; Stack Pointer Initialize TXSP LDM LDM : : : : R0, #0 R0DD,#1000_0010B ; Normal Port 0 ; Normal Port Direction
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8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and OSD memory.
0000H 00C0H 0100H 0200H 0300H RAM (256 bytes) 0400H 0500H RAM (256 bytes) 0600H 063FH RAM (64 bytes) Empty area 0A00H OSD RAM (192 bytes) PageA Page5 Page6 RAM (256 bytes) Page3 Page4
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
RAM (192 bytes) Page0 Peripheral Reg. (64 bytes) RAM (256 bytes) Stack area RAM (256 bytes) Page1 Page2
Example; To write at CKCTLR
LDM CLCTLR,#09H ;Divide ratio /8
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 20.
0AE0H Peripheral Reg. (32 bytes) 0C00H 0C5FH Sprite RAM (96 bytes) PageC
Figure 8-8 Data Memory Map
User Memory The GMS87C4060 has 1,536 x 8 bits for the user memory (RAM). HMS81C4332 has 512 x 8 bit for the user memory (RAM) addressed 000H ~ 23FH except Peripheral Reg. (64 bytes) . HMS81C4308/16/24 has 256 x 8 bit RAM add ressed 000H ~ 1 3FH except periph eral reg ister (0C0h~0FFh) Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The basic control registers are in address range of 00C0H to 00FFH. And OSD control registers are assigned within 0AE0H ~ 0AFFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
Address 00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH 00CEH 00CFH
Symbol R0 R0DD R1 R1DD R2 R2DD R4 R4DD R5 R5DD R6 R6DD FUNC1 FUNC2
R/W R/W W R/W W R/W W R/W W R/W W R/W W W W
Reset Value ???????? 00000000 ???????? 00000000 ???????? 00000000 ???????? 0000---???????? ----0000 ?------0-------0000000 ---00000
Addressing mode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte
Table 8-1Control registers
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0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DEH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E8H 0E9H 0EAH 0EBH 0EEH 0EFH 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F9H 0FAH 0FBH 0FCH 0FDH 0AE0H 0AE1H 0AE2H 0AE3H 0AE4H 0AE5H 0AE6H 0AE8H 0AE9H 0AF0H 0AF1H 0AF3H 0AF4H
TM0 TM2 TDR0 TDR1 TDR2 TDR3 BITR CKCTLR WDTR ICAR ICDR ICSR ICCR1 ICCR2 SIOM SIOR PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5 PWM8H PWM8L PWMCR1 PWMCR2 BUR AIPS ADCM ADR IEDS IMOD IENL IRQL IENH IRQH IDCR IDFS IDR DPGR TMR OSDcon1 OSDcon2 OSDPOL FDWSET EDGEcol OSDLN LHPOS SPVPOS SPHPOS L1ATTR L1VPOS L2ATTR L2VPOS
R/W R/W R/W R/W R/W R/W R W W R/W R/W R/W R/W R/W R/W R/W W W W W W W R/W R/W R/W R/W W W R/W R W R/W R/W R/W R/W R/W R/W R R R/W W R/W R/W W W W R W W W W W W W
-0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 000100000000000 00000000 -0000001 ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? --?????? 00000000 --0-0000 ???????? --000000 --011101 ???????? --000000 --000000 0000000000000000000000 00000000 0000-000 1----001 ???????? ----0000 ???????? 00000000 -0000000 ???????? 01111010 10000111 ---00000 ???????? ???????? ???????? ???????? ???????? ???????? ????????
byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte byte, bit byte, bit byte byte byte byte byte byte byte byte byte byte byte
1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
Table 8-1Control registers
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8.4 Addressing Mode
The GMS800 series uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
35H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0
E551: C535 LDA 35H;A RAM[35H]
A
~ ~ ~ ~
C5 35
data A
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
FE10: 0435 ADC
MEMORY
0E550H 0E551H
(4) Absolute Addressing !abs
#35H
0FE10H
04 35
A+35H+C A
Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
F100: 0735F0 ADC!0F035H ;A ROM[0F035H]
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit direct page accessable register (DPGR) and 8-bit immediate data. Example: G=1, DPGR=0CH
F100: E45535 LDM 35H,#55H ~ ~
0F100H 0F101H 0C35H data data 55H 0F102H 07 35 F0 0F035H data
A
~ ~
A+data+C A
P
address: 0F035
~ ~
~ ~
0F100H 0F101H 0F102H E4 55 35
A
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and DPGR.
F100: 983501 INC!0135H ;A ROM[135H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
F100: DB LDA {X}+
135H
data
A
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 01
A
data+1 data
35H
data
A
~ ~
data A
~ ~
0F100H DB
address: 0135
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, DPGR=03H
E550: D4 LDA {X};ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
E550: C645 LDA 45H+X
315H
data
A
~ ~
data A
~ ~
0E550H D4
3AH
data
A
~ ~
0E550H 0E551H C6 45
~ ~
A
data A
45H+0F5H=13AH
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
F100: D500FA LDA !0FA00H+Y
FA00: 3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
A jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair m em ory w hich is deter mined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
FA00: 1625 ADC [25H+X]
~ ~
0FA55H data
~ ~
A
data A
A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~A ~
0E005H
~ ~
25 + X(10) = 35H
~ ~
16 25
A A + data + C A
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
FA00: 1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
FA00: 1F25E0 JMP [!0C025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
A
0E005 H + Y(10) = 0E015H
~ ~
~ ~
NEXT
A
jump to address 0E30AH
~ ~
0E725 H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25
~ ~
A A + data + C A
E0
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9. I/O PORTS
The GMS87C4060 has digital ports (R0, R1, R2, R4, R5 and R6) and OSD ports (R,G,B), but HMS81C43XX has R1, R2, R4, R5 and OSD ports (R,G,B) These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, in a initial reset state, R ports are used as a general purpose digital port.
9.1 Registers for Port
Port Data Registers The Port Data Registers in I/O buffer in each R ports are represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal Port Direction Registers All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction reg0C8H 0C9H
ister) during initial setting as shown in Figure 9-1 . All the port direction registers in the HMS81C43XX/ GMS87C4060 have 0 written to them by reset function. On the other hand, its initial status is input.
WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H R0 DATA R0 DIRECTION 01010101 76543210 BIT
~ ~
R4 DATA R4 DIRECTION
~ ~
IO IOIO I O PORT 76543210 I : INPUT PORT O : OUTPUT PORT
Figure 9-1 Example of port I/O assignment
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9.2 I/O Ports Configuration
R0 Ports R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). The control registers for R0 are shown below.
R1 Direction Register R0 Data Register
RW RW R06 RW R05 RW R04 RW R03
The control registers for R1 are shown below.
R1 Data Register
RW RW R16 RW R15 RW R14 RW R13
ADDRESS : 00C2H RESET VALUE : Undefined
RW R12 RW R11 RW R10
R1
R17
ADDRESS : 00C0 H RESET VALUE : Undefined
RW R02 RW R01 RW R00
ADDRESS : 00C3H RESET VALUE : 0000 0000b
W W W W W W
W
W
R1DD Port Direction 0: Input 1: Output A/D Convertor mode Register
RW RW RW
R0
R07
R0 Direction Register
W W W W W
ADDRESS : 00C1H RESET VALUE : 0000 0000b
W W W
R0DD Port Direction 0: Input 1: Output ADCM A/D Enable 0: Disable 1: Enable
ADDRESS : 00F0H RESET VALUE : --01 1101b
RW RW R
ADEN ADS2 ADS1 ADS0 ADST ADSF
In addition, Port R0 is only digital I/O. After reset, R0DD value is "0", R0 acts as normal digital input port.
R1 Ports R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C3H). R1 port have secondary functions as following table.
Port Pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate Function AN0 (A/D input 0) AN1 (A/D input 1) AN2 (A/D input 2) AN3 (A/D input 3) AN4 (A/D input 4) AN5 (A/D input 5) VD (Vertical Sync. input) HD (Horizontal Sync. input)
W
A/D Status 0: Busy A/D Port select 1: Finish 000: AN0 001: AN1 A/D Start 010: AN2 0: Ignore 011: AN3 1: A/D start 100: AN4 101: AN5 110: AN6 111: No Analog port ADDRESS : 00EFH RESET VALUE : --00 0000b
W W W
Analog input pin selector Register
W W
AIPS Port Property 0: Digital I/O 1: Analog Input Port function select Register 2
W W VDS
ADDRESS : 00CFH RESET VALUE : ---0 0000b
W YMS W YSS W IS
FUNC2
HDS
R16/VD select 0: R16 I/O 1: VD Input R17/HD select 0: R17 I/O 1: HD Input
Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, R1 port acts as normal digital input port. The way to select alternate function such as A/D input or HD,VD will be shown in each peripheral section.
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R2 Port R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 00C5H). The control registers for R2 are shown below.
R2 Data Register
RW RW R26 RW R25 RW R24 RW R23
R4 Port R4 is consrutced with 4-bit Open drain Output port and 4bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0C9H). The control registers for R4 are shown below.
ADDRESS : 00C4 H RESET VALUE : Undefined
RW R22 RW R21 RW RW RW R46 RW R45 RW R44 RW R43 R20
R4 Data Register
ADDRESS : 00C8H RESET VALUE : Undefined
RW R42 RW R41 RW R40
R2
R27
R4 ADDRESS : 00C5H RESET VALUE : 0000 0000b
W W W W W W
R47
R2 Direction Register
W W
R4 Direction Register
W W W W W
ADDRESS : 00C9H RESET VALUE : 0000 ----b
W W W
R2DD Port Direction 0: Input 1: Output Serial I/O mode Register
RW IOSW SIOM Serial I/O 0: Serial In 1: Serial Out RW SM1 RW SM0 RW
R4DD Port Direction 0: Input 1: Output I2C Control Register 1
RW RW RW ALS RW ESO BSW1 BSW0
ADDRESS : 00DEH RESET VALUE : -000 0001b
RW RW R SCK1 SCK0 SIOST SIOSF
ADDRESS : 00DBH RESET VALUE : 00-0 0000b
RW BC2 RW BC1 RW BC0
ICCR1
Clock select 00: PS3 01: PS4 10: PS5 11: External SM1 SM0 Mode 0 0 Send 1 0 Receive 0 1 1 1
Seriial Status 0: Busy 1: Finish Serial Start 0: Ignore 1: Serial start R21 R21 Sclk Sclk R21 R22 R22 Sout R22 R22 R23 R23 R23 Sin R23
I2C enable 0: Disable 1: Enable
Bit count 000b (8bit) 001b~111b (1~7bit)
Slave address identification 0: Accept (Addressing format) 1: Decline (Free data format) BSW1 BSW0 0 0 1 0 0 1 1 1 R44 R44 SCL0 R44 SCL R45 R45/PWM4 R45/PWM4 SCL1 SCL R46 R46 SDA0 R46 SDA R47 R47/PWM5 R47/PWM5 SDA1 SDA
Port function select Register 1
W W W W
ADDRESS : 00CEH RESET VALUE : -000 0000b
W W W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
PWM control Register 1
RW RW EN4 RW EN3 RW EN2 RW EN1
ADDRESS : 00EAH RESET VALUE : 0000 0000b
RW EN0 RW EN8 RW CNT
R27/EC3 0: R27 1: EC3 R25/EC2 0: R25 1: EC2
R20/INT2 R24/INT3 0: R20 1: INT2 R26/INT4 0: R24 1: INT3 0: R26 1: INT4 ADDRESS : 00F2H RESET VALUE : --00 0000b
W W W
PWMCR1
EN5
EN5,4,3,2,1 : R47,45,43,42,41,40 0: R4x acts normal digital port 1: R4x acts PWM output port
14/8bit PWM count 0: Count start 1: Count stop R51/PWM8 select 0: R51 1: PWM8
Ext. interrupt edge selection Register
W W W
IEDS
IED2H IED2L IED1H IED1L IED0H IED0L
INT2
00: Ignore edge 01: Falling edge 10: Rising edge 11: Falling/Rising edge
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R5 Port R5 is an 7-bit port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5DD register (address 0CBH). The control registers for R5 are shown below
R5 Data Register
RW RW R55 RW R54 RW R53
R6 Port R6 is an 1-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6DD register (address 0CDH). The control registers for R6 are shown below
R6 Data Register
RW
ADDRESS : 00CAH RESET VALUE : Undefined
RW R52 RW R51 RW R50
ADDRESS : 00CCH RESET VALUE : Undefined
R5
R56
R6
R67
R5 Direction Register
W
ADDRESS : 00CBH RESET VALUE : ---- 0000b
W W W
R6 Direction Register
W
ADDRESS : 00CDH RESET VALUE : 0--- ----b
R5DD Port Direction 0: Input 1: Output Port function select Register 1
W W W W
R6DD Port Direction 0: Input 1: Output Port function select Register 1
W W W W
ADDRESS : 00CEH RESET VALUE : -000 0000b
W W W
ADDRESS : 00CEH RESET VALUE : -000 0000b
W W W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
FUNC1 R52/INT0 0: R52 1: INT0
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
R67/INT1 0: R67 1: INT1 Ext. interrupt edge selection Register
W W W
Port function select Register 2
W W VDS
ADDRESS : 00CFH RESET VALUE : ---0 0000b
W YMS W YSS W IS
ADDRESS : 00F2H RESET VALUE : --00 0000b
W W W
FUNC2
HDS
IEDS R54/YM R55/YS R56/I 0: R56 0: R55 0: R56 1: YM Output 1: YS Output 1: I Output PWM control Register 2
RW RW
IED2H IED2L IED1H IED1L IED0H IED0L
INT1
ADDRESS : 00EBH RESET VALUE : --0- 0000b
RW RW EN7 RW EN6 POL2 POL1
00: Ignore edge 01: Falling edge 10: Rising edge 11: Falling/Rising edge
PWMCR2
BUZS
R50/BUZZ 0: R50 1: BUZZ Ext. interrupt edge selection Register
W W W
ADDRESS : 00F2H RESET VALUE : --00 0000b
W W W
IEDS
IED2H IED2L IED1H IED1L IED0H IED0L
00: Ignore edge INT2 01: Falling edge 10: Rising edge 11: Falling/Rising edge
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10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. The system clock can also be obtained from the external oscillator. The clock generator produces the system clocks forming clock pulse, which are supplied to the CPU and the peripheral hardware.
Main clock 3.6MHz 4MHz 8MHz Minimum instruction cycle time (ex:NOP ; fex 4clock is needed) 1,111nS 1,000nS 500nS
To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by bit 4 of the peripheral clock enable register (ENPCK).
OSC Circuit
fEX
Clock pulse Generator
Internal system clock
P R E SC A LE R ENPCK
[0D6H] CKCTLR
WDT ENPCK BTCL BTS2 BTS1 BTS0 ON
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
Clock control register
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1024
/2048
Figure 10-1 Block Diagram of Clock Generator
/1
Peripheral clock
Note: On the initial reset, all peripherals are run because peripheral clock is supplied to each function block. If you want to see more details, see Clock Control Register (CKCTLR).
Clock control register
W W W
ADDRESS : 00D6H RESET VALUE : --01 0111b
W W W WDT ENPCK BTCL BTS2 BTS1 BTS0 ON
CKCTLR Test mode register
W W W W W
ADDRESS : 00FDH RESET VALUE : 0000 0000 b
W W W
Watch-dog timer select 0: Normal 6bit timer 1: Watch-dog timer
TMR
Peri. Clock 0: Stop 1: Supply
B.I.T Clock B.I.T set 0: Free run 1: B.I.T clear
0000 0110b Normal operation mode
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11. TIMER
11.1 Basic Interval Timer
The HMS81C43XX/GMS87C4060 has one 8-bit Basic Interval Timer that is free-run and can not be stopped. Block diagram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 00D6H is read as a BITR and written to CKCTLR..
PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11
fex/210 fex/211
fex/24 fex/25 fex/26 fex/27 fex/28 fex/29
MUX
source clock
8-bit up-counter overflow
BITR
[0D6H]
BITIF
Basic Interval Timer Interrupt
Watchdog timer clock (WDTCK)
clear 3 BITCK
BTCL
Select Input clock Clock control register [0D6H] CKCTLR
WDT ENPCK BTCL BTS2 BTS1 BTS0 ON
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Source clock BTS2~0 P re-S caler output 000 001 010 011 100 101 110 111 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 fex/24 fex/25 fex/26 fex/27 fex/28 fex/29 fex/210 fex/211
Interrupt (overflow) Period At fex=8MHz 0.512 mS 1.024 2.048 4.096 8.192 16.384 32.768 65.536
Table 11-1 Basic Interval Timer Interrupt Time
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HMS81C43XX / GMS87C4060
W
W
W
W
W
W
CKCTLR
WDT ENPCK BTCL BTS2 BTS1 BTS0 ON
ADDRESS : 00D6H RESET VALUE : --01 0111b
Watch-dog timer select 0: Normal 6bit timer 1: Watch-dog timer
Peri. Clock 0: Stop 1: Supply
B.I.T Clock B.I.T set 0: Free run 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after 1 machine cycle
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
R R R R R R R R
BITR
8-BIT BINARY COUNTER
ADDRESS: 00D6H INITIAL VALUE: Undefined
Figure 11-2 BITR: Basic Interval Timer Mode Register
11.2 Timer 0, 1
Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 11-3 . These Timers can run separated 8bit timer or combined 16bit timer. These timers are operated by internal clock. The contents of TDR1 are compared with the contents of up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared.
Note: You can read Timer 0, Timer 1 value from TDR0 or TDR1. But if you write data to TDR0 or TDR1, it changes Timer 0 or Timer 1 modulo data, not Timer value.
The control registers for Timer 0,1 are shown below.
Timer mode register 0
RW RW RW RW
ADDRESS : 00D0H RESET VALUE : -000 0000b
RW RW RW T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0
TM0
T1ST
Timer 1 start 0: Count Hold 1: Count Clear and Start
Timer 1 input clock 00: Timer 0 overflow (16bit mode) Timer 0 control 01: PS2 (fex / 22) 0: Count Hold 10: PS4 (fex / 24) 1: Count Continue Timer 0 start 11: PS6 (fex / 26) 0: Count Hold 1: Count Clear and Start Timer 0 data register
RW RW RW RW RW
Timer 0 input clock 00: PS2 (fex / 22) 01: PS4 (fex / 24) 10: PS6 (fex / 26) 11: PS8 (fex / 28)
ADDRESS : 00D2H RESET VALUE : Undefined
RW RW RW
The content of TDR0, TDR1 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 0 or Timer 1 can not count up forever.
TDR0 Timer 1 data register
RW RW RW RW RW
ADDRESS : 00D3H RESET VALUE : Undefined
RW RW RW
TDR1
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Internal bus line TM0 TDR0 TDR1
T0CN
8bit Comparator
T0IF Timer 0 Timer 1
8bit Comparator
T1IF
PS2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
NC PS2 PS4 PS6
MUX
T1ST
Figure 11-3 Simplified Block Diagram of 8bit Timer0, 1
TDR0
disable enable
clear & start stop
up -c
ou nt
~ ~
~ ~
TIME Timer 0 (T0IF) Interrupt
Occur interrupt Occur interrupt
T0ST Start & Stop T0CN Control count
T0ST = 0
T0ST = 1
T0CN = 1 T0CN = 0
Figure 11-4 Count Example of Timer
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Internal bus line TM0 00 T0CN TDR0 TDR1
16bit Comparator
T1IF Timer 0 Timer 1
PS2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1
11.3 Timer / Event Counter 2, 3
Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 11-5 . These Timers have two operating modes. One is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin R25/EC2, R27/EC3. These Timers can run separated 8bit timer or combined 16bit timer.
Note: You can read Timer 2, Timer 3 value from TDR2 or TDR3. But if you write data to TDR2 or TDR3, it changes Timer 2 or Timer 3 modulo data, not Timer value.
The control registers for Timer 2,3 are shown below
Timer mode register 2
RW RW RW RW
ADDRESS : 00D1H RESET VALUE : -000 0000b
RW RW RW T2CN T2SL1 T2SL0
TM2
T3ST
T3SL1 T3SL0 T2ST
Timer 3 start 0: Count Hold 1: Count Clear and Start
Timer 3 input clock 00: Timer 2 overflow (16bit mode) Timer 2 control 01: PS2 (fex / 22) 0: Count Hold 10: PS4 (fex / 24) 1: Count Continue Timer 2 start 11: PS6 (fex / 26) 0: Count Hold 1: Count Clear and Start Timer 2 data register
RW RW RW RW RW
Timer 2 input clock 00: PS2 (fex / 22) 01: PS4 (fex / 24) 10: PS6 (fex / 26) 11: PS8 (fex / 28)
ADDRESS : 00D4H RESET VALUE : Undefined
RW RW RW
The content of TDR2, TDR3 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 2 or Timer 3 can not count up forever.
TDR2 Timer 3 data register
RW RW RW RW RW
ADDRESS : 00D5H RESET VALUE : Undefined
RW RW RW
TDR3 Port function select Register 1
W W W W
ADDRESS : 00CEH RESET VALUE : -000 0000b
W W W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
R27/EC3 0: R27 1: EC3
R25/EC2 0: R25 1: EC2
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Internal bus line TM2 TDR2 TDR3
T2CN
8bit Comparator
T2IF Timer 2 Timer 3
8bit Comparator
T3IF
EC2 PS2 PS4 PS6
MUX Clock T2ST Clear Clock Clear
NC EC3 PS2 PS4
MUX
T3ST
Figure 11-6 Simplified Block Diagram of 8bit Timer/Event Counter 2,3
TDR2
disable enable
clear & start stop
up -c
ou nt
~ ~
~ ~
TIME Timer 2 (T2IF) Interrupt
Occur interrupt Occur interrupt
T2ST Start & Stop T2CN Control count
T2ST = 0
T2ST = 1
T2CN = 1 T2CN = 0
Figure 11-7 Count Example of Timer / Event counter
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HMS81C43XX / GMS87C4060
Internal bus line TM2 00 T0CN TDR2 TDR3
16bit Comparator
T3IF Timer 2 Timer 3
EC2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3
Timer Mode In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn (n=0~3) are compared with the contents of up-counter, Timer n. If match is found, a timer
Start count
n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you want
Source clock
~ ~ ~~~~ ~~~~
N-2 N-1 N 0 1 3 4
Up-counter
0
1
2
3
2
TDRn (n=0~3) TnIF (n=0~3) interrupt
N
Match Detect
Counter Clear
Figure 11-9 Timer Mode Timing Chart
~ ~
Event counter Mode In event timer mode, counting up is started by an external trigger. This trigger means falling edge of the ECn (n=2~3) pin input. Source clock is used as an internal clock selected with TM2. The contents of TDRn are compared with the contents of the up-counter. If a match is found, an TnIF interrupt is generated, and the counter is cleared to 00 H. The counter is restarted by the falling edge of the ECn pin in-
put. The maximum frequency applied to the ECn pin is fex/2 [Hz] in main clock mode. In order to use event counter function, the bit EC2S, EC3 of the Port Function Select Register1 FUNC1(address 0CEH) is required to be set to "1". After reset, the value of TDRn is undefined, it should be
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initialized to between 01H~FFH not to 00H
Start count
ECn (n=2~3) pin
~ ~ ~~ ~~
Up-counter
0
1
2
N-1
N
0
1
2
~~ ~~
TDRn (n=2~3) TnIF (n=2~3) interrupt
N
Figure 11-10 Event Counter Mode Timing Chart
~ ~
The interval period of Timer is calculated as below equation.
------ = - x

x

TDR2 TDR2=n
n n-1 n-2
PCP
~ ~
co un t
~ ~
8 7 6
up -
~ ~
2 1 0
5 4 3
TIME
Interrupt period = PCP x n
Timer 2 (T2IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 11-11 Count Example of Timer / Event counter
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HMS81C43XX / GMS87C4060
TDR2
disable enable
clear & start stop
up -c ou nt
~ ~
~ ~
TIME Timer 2 (T2IF) Interrupt
Occur interrupt Occur interrupt
T2ST Start & Stop T2CN Control count
T2ST = 0
T2ST = 1
T2CN = 1 T2CN = 0
Figure 11-12 Count Operation of Timer / Event counter
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12. A/D Converter
The A/D convertor circuit is shown in Figure 12-1 . The A/D convertor circuit consists of the comparator and c o n t r o l r eg i s te r A I P S ( 0 0 E F H ) , A D C M ( 0 0 F 0 H ) , ADR(00F1H). The AIPS register select normal port or analog input. The ADCM register control A/D converter's activity. The ADR register stores A/D converted 8bit result. The more details are shown Figure 12-2 .
ADCM [F0H]
ADEN ADS2 ADS1 ADS0 ADST ADSF
ADR [F1H]
IFA Control circuit port select AN0 AN1 AN2 AN3 AN4 AN5 Register ladder MUX Vref S/H
Comparator
+ -
Succesive Approximation Circuit
Figure 12-1 Block Diagram of A/D convertor circuit
Control The HMS81C43XX/GMS87C4060 contains a A/D converter module which has six analog inputs. 1. First of all, you have to select analog input pin by set the ADCM and AIPS. 2. Set ADEN (A/D enable bit : ADCM bit5). 3. Set ADST (A/D start bit : ADCM bit1). We recommend you do not set ADEN and ADST at once, it makes worse A/D converted result. 4. ADST bit will be cleared automatically 1cycle after you set this. Example:
: ; Set AIPS, change ? to what you want ; 0 : digital port
1 : analog port LDM AIPS,#00??????b ; Set ADEN, xxx is analog port number LDM ADCM,#001xxx00b ; or "SET1 ADEN" ; Set ADST, xxx is analog port number LDM ADCM,#001xxx10b ; or "SET1 ADST" : :
;
5. After A/D conversion is completed, ADSF bit and interrupt flag IFA will be set. (A/D conversion takes 36 machine cycle : 9uS when fex=8MHz).
Note: Make sure AIPS bits, if you using a port which is set digital input by AIPS, analog voltage will be flow into MCU internal logic not A/D converter. Sometimes device or port is damaged permanently.
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HMS81C43XX / GMS87C4060
A/D Convertor mode Register
RW RW RW
ADDRESS : 00F0H RESET VALUE : --01 1101b
RW RW R
ADCM A/D Enable 0: Disable 1: Enable
ADEN ADS2 ADS1 ADS0 ADST ADSF
A/D Status 0: Busy A/D Port select 1: Finish 000: AN0 001: AN1 A/D Start 010: AN2 0: Ignore 011: AN3 1: A/D start 100: AN4 101: AN5 11x: No Analog port
A/D Result Register
R R R R R
ADDRESS : 00F1H RESET VALUE : Undefined
R R R
ADR 8bit result is stored Analog input pin selector Register
W W W
ADDRESS : 00EFH RESET VALUE : --00 0000b
W W W
AIPS Port Property 0: Digital I/O 1: Analog Input
Figure 12-2 A/D convertor Registers
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13. Serial I/O
The Serial I/O circuit is shown in Figure 13-1 . The Serial I/O circuit consists of the octal counter, SIOR(DFH), SIOM(DEH). The SIOR register stores received data or data which will be transfered. The SIOM register controls serial communication mode, speed, start, etc. The more details about registers are shown Figure 13-2 .
SIOM [DEH]
IOSW SM1
SM0
SCK1 SCK0 SIOST SIOSF
SIOR [DFH]
D7
D6
D5
D4
D3
D2
D1
D0
PS3 PS4 PS5 Exclk MUX Control Circuit Octal counter IFSIO
Sclk
Sout Sin
1 MUX 0
Figure 13-1 Block Diagram of Serial I/O circuit
Control The HMS81C43XX/GMS87C4060 contains a Synchronous type Serial I/O module. 1. You have to select serial I/O pins by set the SM1~0.
Port select SM1 SM0 0 0 1 1 0 1 0 1 Function R21 Send Receive R21 Sclk Sclk R21 R22 R22 Sout R22 R22 R23 R23 R23 Sin R23
2. You have to select serial communication clock by set the SCK1~0.
SCK1 0 0 1 1 SCK0 0 1 0 1 Selected Clock PS3 PS4 PS5 External clock Ex: Frequency (fex=8MHz) 1uS 2uS 4uS User define
3. If you want to send data, write it to SIOR. Or not skip this. 4. Start serial communication by set SIOST(Serial I/O start, SIOM bit1).
Note: Sout pin can handle serial data output or serial data input. You can input serial data to Sout pin when IOSW bit is 1. But Sin pin is dedicated serial data input pin.
5. After serial communication is completed, SIOSF bit and
interrupt flag IFSIO will be set.
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HMS81C43XX / GMS87C4060
Serial I/O mode Register
RW RW RW SM0 RW
ADDRESS : 0DEH RESET VALUE : -000 0001b
RW RW R SCK1 SCK0 SIOST SIOSF
SIOM
IOSW SM1
Serial I/O Interrupt Service routine
Input select 0: Sin 1: Sout
Clock Select
Serial Status 0: Busy 1: Finish Serial COMM. Start 0: Ignore 1: COMM. start
SIOSF=1? Yes
No
Send / Receive
Abnormal operation Serial I/O data Register
RW RW D6 RW D5 RW D4 RW D3
ADDRESS : 0DFH RESET VALUE : Undefined
RW D2 RW D1 RW D0
SE=0 // SE : Interrupt enable bit Write SIOM // SR : Interrupt request flag No
SIOR
D7
Figure 13-2 Serial I/O Registers
SR=0? Yes Normal operation Overrun error
Figure 13-3 Example for serial I/O check by S/W
Input clock
Sclk
SIOST
Sout
D0
D1
D2
D3
D4
D5
D6
D7
Sin
D0
D1
D2
D3
D4
D5
D6
D7
IFSIO
Figure 13-4 Serial I/O Timing Chart
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14. Pulse Width Modulation (PWM)
The PWM circuit is shown in Figure 14-1 , Figure .
Example (fex =8MHz) Resolution Input Clock Frame cycle 14bit PWM 0.5uS 2MHz 8,192uS 8bit PWM 4uS 250KHz 1,024uS
PWMCR2 [EBH] PWMCR1 [EAH]
The PWM circuit consists of the counter, comparator, Data register. The PWM control registers are PWMR7~0, PWMCR2~1, PWM8H, PWM8L. The more details about registers are shown Figure 14-2 .
EN5 CNTB
EN4 EN3 EN2 EN1 EN0
PWMR5 [E5H] PWMR4 [E4 H]
PWM5 PWM4 PWM3
PWMR3 [E3H] PWM2 PWMR2 [E2H] PWMR1 [E1H] PWMR0 [E0 H] PWM0 8bit comparator PWM1
PS5 8bit counter
IF1Frame
Figure 14-1 8bit register (PWM7~0) circuit
Internal Control
PWMCR2 [EBH]
PWMCR1 [EAH]
CNTB PWMR8L 6bit [E9H] PWM8
PWMR8H 8bit [E8H]
MSB
14bit comparator
LSB
PS2 14bit counter
Figure 14-2 14bit register (PWM8) circuit
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HMS81C43XX / GMS87C4060
8bit PWM Control The HMS81C43XX/GMS87C4060 contains a one 14bit PWM and six 8bit PWM module. 1. 8bit PWM0~5 is wholy same internal circuit, but PWM0~5 output port is NMOS open drain. 2. Al l PWM polarity has the same by POL2's value. 3. Calulate Frame cycle and Pulse width is as following. PWM Frame Cycle = 2 13/ fex (Sec) PWM Width = (PWMRn+1) * 2 5 / f ex (n=0~5) Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5)
5. CNTB controls all PWM counter enable. If CNTB=0, Counter is enabled. 14bit PWM Control 1. 14bit PWM's operation concept is not the same as 8bit PWM. 1 PWM frame contains 64 sub PWMs. PWM8H : Set sub PWM's basic Pulse Width. PWM8L : Number of sub PWM which is added 1 clock. 2. PWM polarity is selected by POL1's value. If POL1=0, Positive Polarity. 3. Calulate Frame cycle and Pulse width is as following. Main PWM Frame Cycle = 216/ fex (Sec). Sub PWM Frame Cycle = Main Frame Cycle / 64. 4. Table 14-1, "PWM8L and Sub frame matching table," on page 48 show PWM8L function.
Bit value Sub frame number which is added 1 clock 32 16, 48 8, 24, 40, 56 4, 12, 20, 28, 36, 44, 52, 60 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 Pulse count 1 2 4 8 16
Positive Polarity (POL2=0)
Negative Polarity (POL2=1)
1 2
1 2
1. Frame cycle 2. Pulse Width
if Bit0=1 if Bit1=1
Figure 14-3 Wave form example for 8bit PWM
if Bit2=1 if Bit3=1 if Bit4=1
4. PWM output is enabled during ENn(n=0~5) bit (See PWMCR1~2) contains 1.
PWM Data Register
W W D6 W D5 W D4 W D3
ADDRESS : 0E0~E5H RESET VALUE : Undefined
W D2 W D1 W D0
if Bit5=1
32
PWMR0~5
D7
PWM control Register 1
RW RW EN4 RW EN3 RW EN2 RW EN1
ADDRESS : 0EAH RESET VALUE : 0000 0000 b
RW EN0 RW EN8 RW CNTB
Table 14-1 PWM8L and Sub frame matching table
PWMCR1
EN5
EN5,4,3,2,1 : R47,45,43,42,41,40 0: R4x acts normal digital port 1: R4x acts PWM output port
Main PWM Frame 14bit Counter enable 0: Counter run 1: Counter stop ADDRESS : 0EBH RESET VALUE : --0- 00--b 012 61 62 63
.....
PWM control Register 2
RW RW
RW
Sub PWM Frame
PWMCR2
BUZS
POL2 POL1
8bit PWM Polarity 0: Positive (PWM from Rising edge) 1: Negative (PWM from Rising edge)
Sub PWM Frame which is added 1 clock
1 clock width : PS2
Figure 14-4 8bit PWM Registers
Figure 14-5 Wave form example for 14bit PWM
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5. PWM output is enabled during EN8 bit contains 1.
PWM Width Data Register
RW RW D6 RW D5 RW D4 RW D3
ADDRESS : 0E8H RESET VALUE : Undefined
RW D2 RW D1 RW D0
6. CNTB controls PWM counter enable. If CNTB=0, Counter is enabled.
PWM8H
D7
PWM Sub-pulse count Register
RW RW D4 RW D3
ADDRESS : 0E9H RESET VALUE : Undefined
RW D2 RW D1 RW D0
PWM8L
D5
PWM control Register 1
RW RW EN4 RW EN3 RW EN2 RW EN1
ADDRESS : 0EAH RESET VALUE : 0000 0000b
RW EN0 RW EN8 RW CNTB
PWMCR1
EN5
14bit PWM enable 0: R51 1: PWM8
14bit Counter enable 0: Counter run 1: Counter stop
PWM control Register 2
RW RW
ADDRESS : 0EBH RESET VALUE : --0- 00--b
RW POL2 POL1
PWMCR2
BUZS
14bit PWM Polarity 0: Positive (PWM from Rising edge) 1: Negative (PWM from Rising edge)
Figure 14-6 14bit PWM Registers
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15. Interrupt interval measurement circuit
The Interrupt interval measurement circuit is shown in Figure 15-1 . The Interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, Edge detector, 8bit counter, measured result storing register, FIFO (9bit, 6level) interrupt, Control register, etc. The more details about registers are shown Figure 15-2 .
IDCR [F9H]
FCLR
IMS
I34H
I34L
ISEL
IDCK
IDST
IDFS [FAH]
DPOL
FOE
FFUL FEMP
PS8 PS9 INT3 INT4
1 MUX 0 1 MUX 0 Edge detector 0 MUX 1 FCLR FIFO (9bit, 6level) Clear 8bit counter Overflow 8 4 INTV
IDR [FBH]
D7
D6
D5
D4
D3
D2
D1
D0
Figure 15-1 Block Diagram of Interrupt interval measurement circuit
Control The HMS81C43XX/GMS87C4060 contains a Interrupt interval measurement module. 1. Select interrupt input pin what you want to measure by set the FUNC1 [00CEH]. 2. Set IDCR [00F9H] : FIFO clear, interrupt mode, interrupt edge select, external interrupt select between INT3 and INT4, sampling clock select. 3. Set IDCR [00F9H] : set IDST to start measuring. 4. Counter value is stored to IDR [00FBH] when selected
edge is detected. After data was written, timer is cleard automatically and it counts continue.
5. You can select interrupt occuring point by set Interrupt
Mode Select bit (IMS), every edge what you selected or FIFO 4 level is filled. 6. If input signal's interval is larger than maximum counter value (0FFH), counter occurring an interrupt and count again from 00H. 7. See Figure 15-4 FIFO operating mechanism.
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Interrupt interval determination control Register
RW RW IMS RW I34H RW I34L
ADDRESS : 00F9H RESET VALUE : 0000 -000b
RW ISEL RW IDCK RW IDST
IDCR
FCLR
Interrupt input
Counter control See Figure 15-3 0: stop 1: Clear & count Int. occuring time 0: Every selected Sampling clock select edge by I34H/L 0: PS9 1: Every FIFO 4level 1: PS8 is filled FIFO clear is filled External Interrupt select 0: Ignored 0: INT3 1: Clear and return to 0 1: INT4 Interrupt interval determination FIFO status Register
R

I34H 1 0 1 1
Item
Symbol
I34L 0 1 1 1
Detecting edge Rising edge Falling edge Both edge Both edge
ADDRESS : 00FAH RESET VALUE : 1--- -001b
R FOE R R FFUL FEMP
Frame Cycle
IDFS
DPOL
Data polarity 0: Data is stored every Falling edge 1: Data is stored every Rising edge FIFO overrun error flag 0: No Error 1: Error detected Interrupt interval determination FIFO Data Register
R R D6 R D5 R D4 R D3
FIFO Empty flag 0: Data filled 1: Empty FIFO Full flag 0: Not full 1: Full ADDRESS : 00FBH RESET VALUE : Undefined
R D2 R D1 R D0
Pulse width

Figure 15-3 Setting for measurement
IDR
D7
Port function select Register 1
W W W W
ADDRESS : 00CEH RESET VALUE : -000 0000b
W W W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
R26/INT4 0: R26 1: INT4
R24/INT3 0: R24 1: INT3
Figure 15-2 Int. interval measurement Registers
1) FIFO storing mechanism FEMP=1, FFUL=0 FEMP=0, FFUL=0 Data 1 FEMP=0, FFUL=0 Data 1 Data 2 FEMP=0, FFUL=1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data in 2) FIFO reading mechanism Read out FEMP=0 Data 1 Data 2 Data in Data in FEMP=0, FFUL=1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 7 Data in Data 6 will be erased. FOE=1 (Over run error) FEMP=0 FEMP=1
Read out
Data 2
Figure 15-4 Example for FIFO operating mechanism
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16. Buzzer driver
The Buzzer driver circuit is shown in Figure 16-1 . The Buzzer driver circuit consists of the 6bit counter, 6bit comparator, Buzzer data register BUR(00EE H). The BUR register controls source clock and output frequency. The more details about registers are shown Figure 16-2 .
BUR [EEH]
BUCK BUCK -1 -0
BU5
BU4
BU3
BU2
BU1
BU0
BUR write
6 6bit Comparator clear PS4 PS5 PS6 PS7 MUX PWMCR2 [EBH]
BUZS POL2 POL1 EN7 EN6
Output Generator
BUZZ
00 01 10 11
6 6bit counter clear
Figure 16-1 Block Diagram of Buzzer driver circuit
Control The HMS81C43XX/GMS87C4060 contains a Buzzer driver module. 1. Select an input clock am ong PS4~7 by set the BUCK1~0 of BUR.
3. Set BUZS bit for output enable. 4. Output waveform is rectagle clock which has 50% duty. 5. You can use this clock for the other purposes.
Buzzer data Register
BUCK1 0 0 1 1
BUCK0 0 1 0 1
Clock source PS4 PS5 PS6 PS7
PWMCR2 BUR
ADDRESS : 0EEH RESET VALUE : ???? ????b
W BU5 W BU4 W BU3 W BU2 W BU1 W BU0
W W BUCK BUCK -1 -0
Input select PWM control Register 2
RW BUZS
Clock Select ADDRESS : 0EBH RESET VALUE : --0- 00--b
RW RW POL2 POL1
2. Select output frequency by change the BU5~0. Output frequency = 1 / (PSx * BUy *2) Hz. x=4~7, y=5~0 See example Table 16-1 and Table 16-2.
Note: Do not select 00H to BU5~0. It means counter stop.
R50/Buzz select 0: R50 1: Buzz output
Figure 16-2 Buzzer driver Registers
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BUR5~0 Dec
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Output frequency (KHz) PS4
250 125 83.333 62.5 50 41.666 35.714 31.25 27.728 25 22.728 20.834 19.23 17.858 16.666 15.626 14.706 13.888 13.158 12.5 11.904 11.364 10.87 10.416 10 9.616 9.26 8.928 8.62 8.334 8.064 7.812 7.576 7.352 7.124 6.944 6.756 6.578 6.41 6.25 6.098 5.952 5.814 5.682 5.556 5.434 5.32 5.208 5.102 5 4.902 4.808 4.716 4.63 4.546 4.464 4.386 4.31 4.238 4.166 4.098 4.032 3.968
BUR5~0 PS7 Dec
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Output frequency (KHz) PS4
375 187.5 125 93.75 75 62.5 53.572 46.875 41.666 37.5 34.09 31.25 28.846 26.786 25 23.436 22.058 20.833 19.736 18.75 17.858 17.045 16.304 15.625 15 14.424 13.888 13.393 12.932 12.5 12.096 11.718 11.364 11.03 10.714 10.416 10.136 9.868 9.616 9.375 9.146 8.929 8.72 8.523 8.334 8.152 7.978 7.813 7.654 7.5 7.352 7.212 7.076 6.944 6.818 6.696 6.578 6.466 6.356 6.25 6.148 6.048 5.952
Hex
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
PS5
125 62.5 42.666 31.25 25 20.888 17.858 15.625 13.888 12.5 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.25 5.952 5.682 5.435 5.208 5 4.808 4.63 4.464 4.31 4.167 4.032 3.906 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.66 2.604 2.551 2.5 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984
PS6
62.5 31.25 20.833 15.625 12.5 10.461 8.928 7.813 6.944 6.25 5.682 5.209 4.808 4.484 4.166 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.718 2.604 2.5 2.404 2.315 2.232 2.155 2.084 2.016 1.953 1.894 1.838 1.786 1.736 1.689 1.645 1.602 1.563 1.524 1.488 1.453 1.421 1.389 1.359 1.33 1.302 1.276 1.25 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992
Hex
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
PS5
187.5 93.75 62.5 46.875 37.5 31.25 26.786 23.436 20.833 18.75 17.045 15.625 14.423 13.393 12.5 11.719 11.029 10.417 9.868 9.375 8.929 8.523 8.152 7.813 7.5 7.212 6.944 6.696 6.466 6.25 6.048 5.859 5.682 5.515 5.357 5.208 5.068 4.934 4.808 4.688 4.573 4.464 4.36 4.261 4.167 4.076 3.989 3.906 3.827 3.75 3.676 3.606 3.538 3.472 3.409 3.348 3.289 3.233 3.178 3.125 3.074 3.024 2.976
PS6
93.75 46.875 31.35 23.436 18.75 15.625 13.393 11.719 10.417 9.375 8.523 7.813 7.211 6.696 6.25 5.859 5.515 5.208 4.934 4.688 4.464 4.261 4.076 3.906 3.75 3.606 3.472 3.348 3.233 3.125 3.024 2.930 2.841 2.757 2.679 2.604 2.534 2.467 2.404 2.344 2.287 2.232 2.18 2.131 2.083 2.038 1.995 1.953 1.913 1.875 1.838 1.802 1.769 1.736 1.705 1.674 1.645 1.616 1.589 1.563 1.537 1.512 1.488
PS7
46.875 23.438 15.625 11.719 9.375 7.813 6.696 5.895 5.208 4.688 4.261 3.906 3.606 3.348 3.125 2.930 2.757 2.604 2.467 2.344 2.232 2.131 2.038 1.953 1.875 1.803 1.736 1.674 1.616 1.563 1.512 1.465 1.420 1.379 1.339 1.302 1.267 1.234 1.202 1.172 1.143 1.116 1.09 1.065 1.042 1.019 0.997 0.977 0.957 0.938 0.919 0.901 0.884 0.868 0.852 0.837 0.822 0.808 0.795 0.781 0.768 0.756 0.744
31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496
Table 16-1 . Example for fex=8MHz
Table 16-2 . Example for fex=12MHz
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17. On Screen Display (OSD)
The On Screen Display circuit is shown in Figure 17-1 . The HMS81C43XX/GMS87C4060 can support 512 OSD chacters, but the last 6 characters (number 506 ~ 511, 1FAH ~ 1FF H) are reserved for IC test and its pattern is fixed by manufacturer. So you can use 506 characters for your own. The OSD circuit consists of the Position attribute register, Line register, Full screen screen control register, sprite control register, sprite position reigster, I/O polarity register, sprite RAM, font ROM, VRAM, etc. The more details about registers are shown Figure 17-2.
Line 1,2 Attribute, Position register L1ATTR [AF0H] L1VPOS [AF1H] L2ATTR [AF3H] L2VPOS [AF4H]
Line register OSDLN [AE5H]
Full screen control register OSDCON1 [AE0H]
Sprite control register OSDCON2 [AE1H] Field detection register FDWSET [AE3H]
Sprite position register SPVPOS [AE8H] SPHPOS [AE9H]
I/O polarity register OSDPOL [AE2H]
Horizontal position register LHPOS [AE6 H]
Color Mode Register Edge color register EDGECOL [AE4H] COLMOD [0AEFH] Mesh Control Register MESHCON [0AEBH] Sprite Control Circuit
OSD Control Circuit
VRAM Sprite RAM
Font ROM R G B I YS YM
OSD, Sprite Generation Circuit
Sprite Control Circuit
Output Control Circuit
HSYNC VSYNC OSC1 OSC2
Synchronization Circuit
Figure 17-1 Block Diagram of On Screen Display circuit
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Character(foreground) - 16 color with half intensity - Color selecting: VRAM n-character bit19~16(see VRAM) Background - 16 color with half intensity - Color selecting :VRAM n-character bit23-20(see VRAM) Characte(foreground) Outline - Controled by LnATTR register(see LnATTR) - 16 color with half intensity - Color selecting : EDGECOL register(see EDGECOL)
Character Shadow - Controlled by LnATTR register(see LnATTR) and VRAM n-character bit11-10(see VRAM) - Color selecting : EDGECOL(see EDGECOL) - 16 color with half intensity Background Shadow - Controlled by VRAM n-character bit15-12 - Color selecting : EDGECOL register(see EDGECOL) - 16 color with half intensity
(No Character Outline Case)
Figure 17-2 OSD Character Font Example
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M 0
Full screen control Register
RW RW RW RW RW
I 0 0 0 0 0 0 1 1 1 1 1 1 1 0
B 0 0 1 1 1 1 0 0 0 0 1 1 1 0
G 1 1 0 0 1 1 0 0 1 1 0 0 1 0
R 0 1 0 1 0 1 0 1 0 1 0 1 1 0
Color GREEN RED+GREEN BLUE BLUE+RED BLUE+GREEN RED+GREEN+BLUE (WHITE) BLACK Half intensity RED Half intensity GREEN Half intencity RED+GREEN Half intensity BLUE Half intensity GREEN+BLUE Half intensity WHITE Half BLANK
ADDRESS : 0AE0H RESET VALUE : 0000 0000 b
RW RW RW
0 0 0 0 0 0 0 0 0 0 0 0 1
OSDCON1
FULM FULI
FULB FULG FULR DLINE DDCLKSTOCK
Full screen background FULLM : Half blank FULLI : Half intensity FULLB : Blue FULLG : Green FULLR : Red
STOP OSD clock 0: Release 1: Stop Double dot clock mode 0: Normal 1: Double Double scan line mode 0: Normal 1: Double ADDRESS : 0AE1H RESET VALUE : 0000 0000 b
Sprite OSD control Register
RW RW RW RW RW
RW
RW
RW OSD ON
OSDCON2
DUSP OBGW ONL2 ONL1 DUSP ENSP PRO CL SD
Double sprite dot clock (Sprite size) 0: x1, x2 1: x2, x4
OSD line 2 0: Off 1: On
Background width per 1 character 0: 12dots 1: 14dots
OSD, Sprite 0: All Off 1: All On Priority 0: Sprite > OSD OSD line 1 1: OSD > Sprite 0: Off Sprite enable 1: On 0: Disable 1: Enable Sprite size 0: Normal 1: Double
Table 17-1 Full Screen Back ground color selection
OSDCON2 bit 0: OSDON It controls OSD, Sprite, Full screen background at once. It does not affect anything to Vsync interrupt and OSD interrupt, etc. bit 1: PROSD It controls screen output priority between sprite and OSD. If its value is 1, OSD hide sprite pattern in overapped area. bit 2: ENSP It enables sprite display. bit 3: DUSP It doubles sprite's horizontal & vertical size during this value is 1. bit 4: ONL1 It enables OSD line 1 display. If it is enabled, OSD interrupt is activated. bit 5: ONL2 It enables OSD line 2 display. If it is enabled, OSD interrupt is activated. bit 6: OBGW It controls character's width. Default width is 12dots. If its value is set, 2 dots (background color) are added both left
Figure 17-3 OSD Control Registers - 1
OSDCON1 bit 0: STOCK It controls OSD LC oscillation. If oscillation is stoped, IC's power consumption is decreased. bit 1: DDCLK If you set this bit to 1, OSD input clock is doubled from LC oscillation. It makes OSD horisontal image size as doubled. bit 2: DLINE If you set this bit to 1, OSD vertical scan counter input clock is doubled from normal state. It makes OSD vertical image size as doubled. bit 7~3: FULLM, I, B, G, R It controls back ground color as below.
M 0 0 I 0 0 B 0 0 G 0 0 R 0 1 Color Transparent (Normal TV) RED
Table 17-1 Full Screen Back ground color selection
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and right side of character. bit 7: DUSPCL It controls sprite's dot clock and scan line speed. It does not affect to OSD. Sprite size is controlled as below.
It controls HS, VS, I, YM, YS, B, G, R port's polarity. If its value is 1, polarity is active high. FDWSET FDWSET (Field Detection Window Seting) register detects the begin of VSync(Vertical Sync.) signal and distinguishs its current field is Even field or Odd field.
DUSPCL 0 0 1 1
DUSP 0 1 0 1
Size Normal x2 Not used x4 12x16 24x32 48x64
Ex2: VSync(Even) Ex1: VSync(Odd)
Table 17-2 Sprite pattern size
FMIN HSync FMAX
I/O Polarity ( initial ) Register
W W POL VS W POLI W POL YM W POL YS
ADDRESS : 0AE2H RESET VALUE : Undefined
W W W POLB POLG POLR
OSDPOL
POL HS
Figure 17-5 FDWSET detection region
POLHS : Hsync. input POLVS : Vsync. input : Half intensity output POLI POLYM : Half blank output : Blue output POLB : Green output POLG : Red output POLR 0: Active Low 1: Active High Field detection Register
W W W W W FPOL
OSD display enable, include the edge color. 0: Off 1: On
The region of FMIN[2:0] ~ FMAX[3:0] is field detection window. FMAX[3:0] can divide the region between HSync(Horizontal Sync.) by 16. You can assume there is 4 bit horizontal counter, for example HCOUNT[3:0] which count 0~15.
ADDRESS : 0AE3H RESET VALUE : 0111 1010b
W W W F M IN 2 ~ 0
FDWSET
FMAX3 ~ 0
If the start of VSync is detected at the window, next field is even. Else if VSync is detected another region of the window, next field is odd. It means start of VSync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it distinguish odd field. And, start of VSync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it distinguish even field. FMIN[2:0], FMAX[3:0] are compared with the horizontal counter in OSD block.
Field detection Maximum pointer
Field detection Minimum pointer Field detection polarity 0: Detect Odd field Masking range : Min.~Max. 1: Detect Even field Detecting range : Min.~Max.
Figure 17-4 OSD Registers - 2
OSDPOL bit7~0 : POL HS, VS, I, YM, YS, B, G, R
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HMS81C43XX / GMS87C4060
Figure 17-7 OSD Registers - 4
Background shadow / edge color Register
W W EDG 2B W EDG 2G W EDG 2R W EDG 1I
ADDRESS : 0AE4H RESET VALUE : Undefined
W EDG 1B W EDG 1G W EDG 1R
L1ATTR bit 0 : LIV8 It is equivalent with L1VPOS's bit 8. See more details in L1VPOS. bit 1: FSC1 It selects character outline and shadow color. If it is 1, it select EDGE2 color in EDGECOL register. Or not, it select EDGE1 color. According to EDGECOL register and this bit character and shadow colors are selected simulteneously bit 3~2: CSZ11~CSZ10 It controls OSD character's size ( x1, x2, x3). You can use this register and DDCLK, DLINE bit, horizontal / vertical size can be controlled (x2, x4, x6). bit 4: ENSH1 It enables line 1's character(foreground) shadow. bit 5: ENOL1 It enables line 1's character(foreground) outline. bit 6: WDSL1 It shows thickness of line 1's shadow and outline.
WDSL 0 ENOL 0 0 1 1 0 0 1 1 ENSH 0 1 0 1 0 1 0 1 outline, shadow No outline, No shadow Thin shadow Thin outline Thin outline Thick shadow No outline, No shadow Thick shadow Thick outline Thick outline Thick shadow
EDGECOL
EDG 2I
Edge 2 color EDGnI EDGnB EDGnG EDGnR OSD line Register
R R
Edge 1 color
: Half Intensity : Blue : Green : Red
n:1~2
ADDRESS : 0AE5H RESET VALUE : ---0 0000b
R R ~ R 0 VLR4
OSDLN
Current displayed OSD line number ( 00000 ~ 11111b : 0 ~ 63 ) OSD line horizontal position Register
W W D6 W D5 W D4 W D3
ADDRESS : 0AE6H RESET VALUE : Undefined
W D2 W D1 W D0
LHPOS
D7
OSD line's horizontal position (00 ~ FFH) Sprite vertical position Register
W W D6 W D5 W D4 W D3
ADDRESS : 0AE8H RESET VALUE : Undefiend
W D2 W D1 W D0
SPVPOS
D7
Sprite's vertical position (00 ~ FFH) Sprite horisontal position Register
W W D6 W D5 W D4 W D3
ADDRESS : 0AE9H RESET VALUE : Undefined
W D2 W D1 W D0
SPHPOS
D7
Sprite's horisontal position (00 ~ FFH)
Figure 17-6 OSD Registers - 3
0 0 0
OSD line 1's attribute Register
W W W W W CSZ 11
ADDRESS : 0AF0 H RESET VALUE : Undefined
W CSZ 10 W W FSC1 L1V8
1 1 1 1
L1ATTR
OBGH WDSL ENOL ENSH 1 1 1 1
Character background height 0: 16dots 1: 18dots
Shadow / Outline Character Shodow width 0: 1dot charcater outline control 0: Disable 1: Propotional control 1: Enable to character 0: Disable size 1: Enable OSD line 1's vertical position Register
W W W L1V5 W L1V4 W L1V3
Character size 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1's color 11: Reserved 1: Edge 2's color
Vertical position L1VPOS's bit8
Table 17-3 Character Outline, Shadow table
bit 7: OBGH1 It controls character's height. Default height is 16dots. If its value is set, 2 dots (background color) are added both top and bottom side of character.
ADDRESS : 0AF1 H RESET VALUE : Undefined
W L1V2 W L1V1 W L1V0
L1VPOS
L1V7 L1V6
OSD line 1's vertical position (include L1V8 : 000 ~ 1FFH)
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L2VPOS L1VPOS It shows OSD line 1's vertical position in 9bit format (LIV8 + L1VPOS, 000 ~ 1FFH). It shows OSD line 2's vertical position. Its function is the same as L1VPOS. COLMOD It controls OSD output mode-RGB direct half intencity.
OSD line 2's attribute Register
W W W W W CSZ 21
ADDRESS : 0AF3 H RESET VALUE : Undefined
W CSZ 20 W W FSC2 L2V8
Color Output Mode Register
ADDRESS : 0AEFH RESET VALUE : Undifined (see Note)
W C16EN
L2ATTR
OBGH WDSL ENOL ENSH 2 2 2 2
Character background height 0: 16dots 1: 18dots
Shadow / Outline width 0: 1dot Out line control 1: Propotional 0: Disable to character 1: Enable size OSD line 2's vertical position Register
W W W L2V5 W L2V4 W
Character size 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1's color 11: Reserved 1: Edge 2's color Shodow control 0: Disable 1: Enable
Vertical position L2VPOS's bit8
COLMOD Fill with `0'
RGB Half intensity enable 1: Enable 0: Enable
Figure 17-10 OSD Register - 7
ADDRESS : 0AF4 H RESET VALUE : Undefined
W L2V2 W L2V1 W L2V0 L2V3
bit 0: C16EN It enables RGB port half intencity output. When this bit is set, RGB port generates half intencity output. Half intencity output is 3.5V voltage level output of RGB port. When you use this bit, you must fill all the other bit with `0'.
Note: When you do not use RGB direct half intncsity output , please initialize this register as 00h.
L2VPOS
L2V7 L2V6
OSD line 2's vertical position (include L2V8 : 000 ~ 1FFH)
Figure 17-8 OSD Registers - 5
OSD line 2's attribute Register
W W W W W CSZ 21
ADDRESS : 0AF3 H RESET VALUE : Undefined
W CSZ 20 W W FSC2 L2V8
L2ATTR
OBGH WDSL ENOL ENSH 2 2 2 2
Character background height 0: 16dots 1: 18dots
Shadow / Outline width 0: 1dot Out line control 1: Propotional 0: Disable to character 1: Enable size OSD line 2's vertical position Register
W W W L2V5 W L2V4 W
Vertical position Character size L2VPOS's bit8 00: Normal Foreground shadow 01: 2 times out line color 10: 3 times 0: Edge 1's color 11: Reserved 1: Edge 2's color Shodow control 0: Disable 1: Enable
MESHCON It controls OSD mesh mode color.
Mesh Mode Color Register ADDRESS : 0AEBH RESET VALUE : See Note
MESHCON ADDRESS : 0AF4 H RESET VALUE : Undefined
W L2V2 W L2V1 W L2V0
L2VPOS
L2V7 L2V6
L2V3
Figure 17-11 OSD Register - 8
OSD line 2's vertical position (include L2V8 : 000 ~ 1FFH)
Note: Please initialize this register as 00h. Though this register is for mesh mode color, it is not used currently.
Figure 17-9 OSD Register - 6
L2ATTR It controls OSD line 2's attributes. Its function is the same as L1ATTR.
VRAM VRAM contains 1 OSD line, 24 character's attributes. Each character's attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, character and character number ( 000H ~ 1FFH, 512 characters
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), etc.
Line No. Character No. 1 2 3 1 : 22 23 24 1 2 3 2 : 22 23 24 Address (bit 23~0) Hexa decimal A40 A41 A42 : A55 A56 A57 AC0 AC1 AC2 : AD5 AD6 AD7 A20 A21 A22 : A35 A36 A37 AA0 AA1 AA2 : AB5 AB6 AB7 A00 A01 A02 : A15 A16 A17 A80 A81 A82 : A95 A96 A97
Bit No. 10 9 8~0
Name BSCUL ENRND CG8~0
Function Select color of left and top side shadow of the background 0: Edge1, 1: Edge2 color Enable character's rounding Character font number ( among 000 ~ 1FFH )
Table 17-5 VRAM (bit15~0) function
Note: if (BSL = 1) & (BSCUL = 0) & (LnATTR,ENSHn = 1), then the right bottom shadow of font character is shifted to 1 dot right side. This shadow effect will continue until that (BSR) of adjacent character attribution become (BSR = 1).
Bit No. & Name
19 18 17 16
Output ( Polarity : Through) R 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y S 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Character color
I 0 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Clear Red Green Yellow Blue Magenta Cyan White Black Half-I,Red Half-I,Green Half-I, Yellow Half-I,Blue Half-I, Magenta Half-I,Cyan Half-I,White
Table 17-4 VRAM memory map
Bit No.
Name
Function Enable right side background shadow. cf. If BSL=1 and BSCUL=1 and LnATTR.ENSHn=1, character's right bottom shadow is shifted to right side by 1dot unit. It acts continued until current character's right side chacter's BSR is set to 1. Enable left side background shadow. Enable bottom side background shadow. Enable top side background shadow. Select color of right and bottom side shadow of the background 0: Edge1, 1: Edge2 color
0 0 0 0 1 1 1 1 1 1 1 1
15
BSR
14 13 12
BSL BSD BSU
11
BSCDR
Table 17-6 VRAM (bit19~16) function Table 17-5 VRAM (bit15~0) function
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this memory can not be accessed by user program.
Bit No. & Name
23 22 21 20
Output ( Polarity : Through) R 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y M 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Y S 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 I 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Back ground color
Charact er code 000H 001H
Address range Upper 4bit 12000 H ~ 1200FH 12010 H ~ 1201FH 12020 H ~ 1202FH : (12000H + xyz0H) ~ (12000H + xyzFH) : 13FD0 H ~ 13FDFH 13FE0 H ~ 13FEFH 13FF0 H ~ 13FFFH Lower 8bit 10000H ~ 1000FH 10010H ~ 1001FH 10020H ~ 1002FH : (10000H + xyz0H) ~ (10000H + xyzFH) : 11FD0H ~ 11FDFH 11FE0H ~ 11FEFH 11FF0H ~ 11FFFH
I 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Clear Red Green Yellow Blue Magenta Cyan White Half blanking Half-I,Green Half-I, Yellow Half-I,Blue Half-I, Magenta Half-I,Cyan Half-I,White Black
002H : xyzH : 1FDH 1FEH 1FFH
Table 17-8 Font ROM memory map
5. A character's address and dot position in font ROM is described in Figure 17-12 .
Address Data 12530H 12531H 12532H 12533H 12534H 12535H 12536H 12537H 12538H 12539H 1253AH 1253BH 1253CH 1253DH 1253EH 1253FH 00H 07H 08H 08H 08H 09H 0BH 08H 08H 08H 08H 08H 08H 08H 07H 00H
MSB
LSB
Address Data 10530H 10531H 10532H 10533H 10534H 10535H 10536H 10537H 10538H 10539H 1053AH 1053BH 1053CH 1053DH 1053EH 1053FH 00H FEH 01H 61H F1H F9H FDH 61H 61H 61H 61H 61H 61H 01H FEH 00H
Table 17-7 VRAM (bit 23 ~ 20) function
Font ROM The HMS81C43XX/GMS87C4060 OSD character size is fixed as 12dots (Horisontal) * 16dots (Vertical). 1. Each horisontal data (12dots) needs 2byte ROM. 2. One character is constructed with 16 horisontal data to vertically. As a result, one character needs 32bytes (2 * 16 bytes). 3. HMS81C4332/GMS87C4060 contains 256/512 characters. Total Font ROM memory size is calulated as 16,384bytes ( 32bytes / character * 512 character ) 4. Font ROM memory is located from 10000H ~ 13FFFH,
Figure 17-12 Example for a character (53H)
Sprite RAM The HMS81C43XX/GMS87C4060 contains a 32bytes (12dot * 16dot) sprite RAM. 1. In view point, sprite is similar to character font but it is not using font ROM. 2. You can selct color by dot unit. 3. Using above 1 and 2, you can make any of patterns what you want by software. For example, arrow cursor or some-
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thing. 4. Sprite position is controlled by sprite position register SPVPOS[0AE8H] and SPHPOS[0AE9H]. 5. Sprite RAM is located 0C00~0CF5H. One sprite RAM byte contains 2 dot's color data. See more details in Table 17-9 ~ Table 17-11.
Column number 00H 01H 02H : 0nH (n=0~F) : 0EH 0FH Row number MSB 0C05 H 0C15 H 0C25 H : 0Cn5 H : 0C05 H 0C05 H ~ ~ ~ ~ ~ ~ ~ ~ ~ LSB 0C00 H 0C10 H 0C20 H : 0Cn0 H : 0C00 H 0C00 H B 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Color Clear Red Green Yellow Blue Black Cyan White
Table 17-11 Sprite RAM Color Table
Test Font HMS81C43XX use first OSD font as test purpose(see Fig17-13). When you design OSD characte font, you incert following font to Font ROM 00h. If you like to use this font originally, please contact us
Table 17-9 Sprite RAM address map
address data MSB 1200H 00H 1201H 00H 1202H 00H 1203H 01H 1204H 03H 1205H 07H 1206H 06H 1207H 06H 1208H 06H 1209H 06H 120AH 06H 120BH 06H 120CH 07H 120DH 03H 120EH 01H 120FH 00H LSB address 1000H 1001H 1002H 1003H 1004H 1005H 1006H 1007H 1008H 1009H 100AH 100BH 100CH 100DH 100EH 100FH data 00H 00H 00H F8H FCH 0EH 06H 06H 06H 06H 06H 06H 0EH FCH F8H 00H
Odd dot color bit No. Function 7 6 B 5 G 4 R 3 -
Even dot color 2 B 1 G 0 R
Table 17-10 A sprite RAM's contents
Figure 17-13 Test Font Pattern
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18. I2C Bus Interface
The I2C Bus interface circuit is shown in Figure 18-1 . The multi-master I2C Bus interface is a serial communications circuit, conforming to the Phlips I2C Bus data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. This multi-master I2C Bus interface circuit consists of the I2C address register, the I 2C data shift register, the I 2C clock control register, the I2C control register, the I2C status register and other control circuits. The more details about registers are shown Figure 18-2 ~ Figure 18-6 .
ICAR [D8H]
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
Address comparator
Interrupt Generation Circuit
IFI2CR
ICDR [D9H] SDA Data Control Circuit Noise Elimination Circuit
D7
D6
D5
D4
D3
D2
D1
D0
BB Circuit
ICSR [00DAH]
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
AL Circuit ICCR1 [00DBH] SCL Clock Control Circuit Noise Elimination Circuit ICCR2 [DCH]
ACLK ACK 1 CCR3~0 B S EL 1 ~ 0 ALS ESO B C 2~0
Bit counter
External clock Clock division
Figure 18-1 Block Diagram of multi-master I2C circuit
Control The HMS81C43XX/GMS87C4060 contains two I2C Bus interface modules. It supports multi-master function, so it contains arbitration lost detection, synchronization function,etc.
ITEM Format Function Philips I2C standard 7bit addressing format Master transmitter Master receiver Slave transmitter Slave receiver
ITEM SCL clock frequency
Function 66.6KHz ~ 500KHz (fex=12MHz) 44.4KHz ~ 333.3KHz (fex=8MHz)
I2C address register It contains slave address (7bit) which is used during slave mode and Read/Write bit. Bit 7 ~ 0 : Slave address 6~0
Note: Bit 7~0 (SAD6~0) store slave address. The address data transmitted from the master is compared with the contents of these bits.
Communication mode
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The more details about its bits are shown Table 18-1.
ADDRESS : 00D8 H RESET VALUE : 0000 0000b
RW RW RW RW RW RW RW R
Bit No.
Name
Function 00: Slave / Receiver mode 01: Slave / Transmitter mode 10: Master / Receiver mode 11: Master / Transmitter mode MST is cleared when - After reset. - After the arbitration lost is occured and 1 byte data transmission is finished. - After stop condition is detected. - When start condition is disabled by start condition duplication preventation function. TRX is cleared when - After reset. - When arbitration lost or stop condition is occured . - When MST is `0', and start condition or ACK non-return mode is detected. BB(Bus busy)bit is 1 during bus is busy. This bit can be written by S/W. its value is `1' by start condition, and cleared by stop condition. PIN(Pending Interrupt Not)bit is interrupt request bit. If I2C interrupt request is issued, its value is 0. PIN is cleared when - After 1 byte trasmission / receive is finished. PIN is set when - After reset. - After write instruction is excuted into I2C data shift register ICDR. - When PIN bit low, the output of SCL is pulled down, So if you want to release SCL, you must perform write instruction CDR. Arbitration lost detection flag. If arbitration lost is detected, AL=1, or 0. Slave address comparison flag. It shows compared result with received address data and I2C address register (ICAR). It is 1, when two of data is same. Table 18-1 Bit function
ICAR
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
Slave address
Figure 18-2 I2C address Register
I2C data shift register [ICDR] The I2C data shift register is an 8bit shift register to store received data and write transmit data. When transmit data is written into this register, it is transfered to the outside from bit7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I 2 C control register (address 00DCH) is "1". The bit counter is reset by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
ADDRESS : 00D9 H RESET VALUE : 0000 0000b
RW RW D6 RW D5 RW D4 RW D3 RW D2 RW D1 RW D0
7 6
MST TRX
5
BB
ICDR
D7
4
PIN
Shift le ft 1-bit e ach S C L
Figure 18-3 Data shift register
I2C status register The I2C status register controls the I2C Bus interface status. The low-order 4bits are read only bits and the high-order 4bits can be read out and written to.
3 AL
2
AAS
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Bit No.
Name
Function General call detection flag. If general call is detected, AD0=1, or not 0. * General call : If received address is all `0' . it is called general call. Last received bit. it is used for receive confirmation. If ACK is returned, LRB=0, or not 1. Table 18-1 Bit function
ADDRESS : 00DBH RESET VALUE : 00-0 0000b
RW RW RW ALS RW ESO RW BC2 RW BC1 RW BC0
1
AD0
ICCR1
BSEL BSEL 1 0
Figure 18-5 I2C control Register 1
0
LRB
I2C control register 2 It controls SCL mode, SCL frequency, etc.
ADDRESS : 00DAH RESET VALUE : 0001 0000b
RW RW TRX RW BB RW PIN R AL R AAS R AD0 R LRB
It contains 8bit data to transmit to external device when trasmitter mode, or received 8bit data from external device when receive mode.
ICSR
MST
Figure 18-4 I2C status Register
Bit No.
Name
Function Select acknowledge clock (ACK) mode. 0: No acknowledge clock mode. acknowledge clock is not generated after data was transmismitted. 1: acknowledge clock mode. acknowledge clock is generated after data was transmismitted. If acknowledge clock is returned, this bit is 0. Or not 1. Not used. Table 18-3 Bit function
I2C control register 1 It controls communication data format.
7 ACLK
Bit No.
Name
Function 6 ACK 1 (fixed)
7 6
I2C connection control. 00: No connection BSEL1 BSEL0 01: SCL1, SDA1 10: SCL2, SDA2 11: SCL1, SDA1, SCL2, SDA2 ALS Data format selection. 0: Addressing format 1: Free data format I2C Bus interface use enable flag 0: Disabled 1: Enabled Bit counter. 000 b: 8bit 001 b~111 b: 1~7bit Table 18-2 Bit function
5
4
3 2 1 0
ESO BC2 BC1 BC0
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Bit No.
Figure 18-7 Interrupt request signal generation timing Name Function SCL Frequency selection SCL frequency = fex / (12 * CCR) Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 fex = 12MHz Not allowed Not allowed 500.0KHz 333.3KHz 250.0KHz 200.0KHz 166.6KHz 142.9KHz 125.0KHz 111.1KHz 100.0KHz 90.0KHz 83.3KHz 76.4KHz 71.4KHz 66.6KHz fex = 8MHz Not allowed Not allowed 333.3KHz 222.2KHz 166.6KHz 133.3KHz 111.1KHz 95.2KHz 83.3KHz 74.1KHz 66.6KHz 60.6KHz 55.5KHz 51.3KHz 47.6KHz 44.4KHz
START condition generation When the ESO bit of the I2C control register (00DBH) is "1", writing to the I2C status register will generate START condition. Refer to Figure 18-8 for the START condition generation timing diagram.
3 2 1 0
CCR3 CCR2 CCR1 CCR0
ICSR write signal (I2C status reg.) SCL
tSETUP
tHOLD
SDA tBB BB (Bus busy) flag
Table 18-3 Bit function
tSETUP : Setup time tHOLD : Hold time tBB : Set time for BB
ADDRESS : 00DCH RESET VALUE : 000- 0000b
RW RW ACK 1 RW RW RW RW
Figure 18-8 START condition generation timing
ICCR2
ACLK
CCR3 CCR2
CCR1 CCR0
Figure 18-6 I2C control Register 2
RESTART condition generation RESTART condition's setting sequence is as followings. 1. Write 020H to I2C status register (ICSR, 00DAH)
SCL
2. Write slave address to I2C data shift register (ICDR, 00D9H) 3. Write 0F0H to I2C status register (ICSR, 00DA H)
PIN
I2C Request
STOP condition generation Writing `C0h' to ICSR will generate a stop condition,
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when ESO (ICCR bit3) is `1' START / STOP condition detect
ICSR write signal (I2C status reg.) SCL
START / STOP condition is detected when Table 18-4 is satisfied.
tSETUP tHOLD
SDA
tBB
SCL release time SCL
BB (Bus busy) flag
tSETUP
tHOLD
tSETUP : Setup time tHOLD : Hold time : Set time for BB tBB
SDA (START)
SDA (STOP)
Figure 18-9 STOP condition generating timing diagram
tSETUP : Setup time tHOLD : Hold time
START / STOP condition generation time is shown Table 18-4.
ITEM Setup time ( tSETUP ) Hold time ( tHOLD ) Set/Reset time for BB flag ( tBB ) Timing SPEC. 3.3uS (n=20cycles) 3.3uS (n=20cycles) 3.0uS (n=18cycles)
Figure 18-10 START / STOP condition detection timing
START / STOP detection time is showed Table 18-5.
ITEM SCL release time Setup time Hold time Timing SPEC. > 2.0uS (n=12cycles) > 1.0uS (n=6cycles) > 1.0uS (n=6cycles)
Table 18-5 Example time ( fex=12MHz ) Table 18-4 Example time ( fex =12MHz )
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Address data communication The first transmitted data from master is compared with I2C address register (ICAR, 00D8 H). At this time R/W is
not compared but it determines next data operation. i.e, transmitting or receiving data
Master -> Slave (with 7bit address)
START Slave addr. ACK 7bit R/W ("0")
Data
ACK
Data
ACK STOP /ACK
Slave -> Master (with 7bit address) Data block from master to slave Data block from slave to master
START Slave addr. ACK 7bit R/W ("1") Data ACK Data ACK STOP
Figure 18-11 Address data communication format
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19. INTERRUPTS
The HMS81C43XX/GMS87C4060 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 16 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 19-2 . Below table shows the Interrupt priority
Reset/Interrupt Hardware Reset External Interrupt 0 OSD Interrupt External Interrupt 1 External Interrupt 2 Timer/Counter 0 Timer/Counter 2 1 Frame Interrupt VSync Interrupt Timer/Counter 1 Timer/Counter 3 Interrupt interval measure Watchdog Timer Basic Interval Timer Serial I/O Interrupt I2C Interrupt Symbol RESET INT0 OSD INT1 INT2 Timer 0 Timer 2 1Frame VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT SIO I2C Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Interrupt Mode Register It controls interrupt priority. It takes only one specified interrupt. Of course, interrupt's priority is fixed by H/W, but sometimes user want to get specified interrupt even if higher priority interrupt was occured. Higher priority interrupt is processed the next time. It contains 2bit data to enable priority selection and 4bit data to select specified interrupt.
Bit No. Name Value 00 01 1X 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function Mode 0: H/W priority Mode 1: S/W priority Interrupt is disabled, even if IE is set. INT0 OSD INT1 INT2 Timer 0 Timer 2 1Frame VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT SIO I2C Not used
5,4
IM1~0
3~0
IP3~0
The External Interrupts can each be transition-activated (1to-0 or 0-to-1 transition). When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. T h e Ti me r /C o u nt er I n te r r up t s ar e ge n er at ed b y TnIF(n=0~3), which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH,IRQL) except Power-on reset and software BRK interrupt.
Table 19-1 Bit function
ADDRESS : 00F3H RESET VALUE : Undefined
RW RW IM0 RW IP3 RW IP2 RW IP1 RW IP0
IMOD
IM1
Figure 19-1 Interrupt Mode Register
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Internal bus line
IENH [00F6H] IRQH [0F7H] INT0 IFOSD INT1 INT2 Timer 0 Timer 2 1 Frame IFVSync
INT0 OSD
Interrupt Enable Register (Higher byte)
IMOD [00F3H]
Bit5
RESET
INT1
BRK
INT2 T0 T2 1Frame VSync T1 T3 INTV WDT BIT SR I2C
To CPU
Priority Control
I Flag Interrupt Master Enable Flag
I-flag is in PSW , it is cleared by "D I", set by "EI" instruction. W hen it goes interrupt service, I-flag is cleared by hardw are, thus any other interrupt are inhibited. W hen interrupt service is completed by "R ETI" instruction, I-flag is set to "1" by hardware.
Timer 1 Timer 3 Intr. interval IFWDT IFBIT IFS IFI2C IRQL [00F5H]
Interrupt Vector Address Generator IENL [00F4H]
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 19-2 Block Diagram of Interrupt
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Interrupt enable registers are shown in Figure 19-4 . These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
R/W
R/W
R/W
R/W INT2
R/W T0
R/W
R/W
R/W LSB
IRQH
INT0 MSB
OSD INT1
T2 1Frame VSync
ADDRESS: 00F7H INITIAL VALUE: 0000 0000b VSync interrupt request flag 1 Frame interrupt request flag Timer / Counter 2 interrupt request flag Timer / Counter 0 interrupt request flag External interrupt 2 interrupt request flag External interrupt 1 interrupt request flag On screen display interrupt request flag External interrupt 0 interrupt request flag
R/W
R/W T3
R/W INTV
R/W WDT
R/W BIT
R/W SR
R/W I2C LSB
IRQL
T1 MSB
ADDRESS: 00F5H INITIAL VALUE: 0000 000-b I 2C interrupt request flag Serial I/O interrupt request flag Basic interval timer interrupt request flag Watch-dog timer interrupt request flag Interrupt interval measurement interrupt request flag (INT3/4) Timer / Counter 3 interrupt request flag Timer / Counter 1 interrupt request flag
Figure 19-3 Interrupt Request Flags
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R/W
R/W
R/W
R/W INT2
R/W T0
R/W
R/W
R/W LSB
IENH
INT0 MSB
OSD INT1
T2 1Frame VSync
ADDRESS: 00F6H INITIAL VALUE: 0000 0000b VSync interrupt enable flag 1Frame interrupt enable flag Timer / Counter 2 interrupt enable flag Timer / Counter 0 interrupt enable flag External interrupt 2 interrupt enable flag External interrupt 1 interrupt enable flag On screen display interrupt enable flag External interrupt 0 interrupt enable flag
R/W
R/W T3
R/W INTV
R/W WDT
R/W BIT
R/W SR
R/W I2C LSB
IENL
T1 MSB
ADDRESS: 00F4H INITIAL VALUE: 0000 000-b I 2C interrupt enable flag Serial I/O interrupt enable flag Basic interval timer interrupt enable flag Watch-dog timer interrupt enable flag Interrupt interval measurement interrupt enable flag (INT3/4) Timer / Counter 3 interrupt enable flag Timer / Counter 1 interrupt enable flag
Figure 19-4 Interrupt Enable Flags
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19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fex (2 s at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decrements 3 times. 4. The entry address of the interrupt service program is read from the vector table address, and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.
System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 19-5 Interrupt Service routine Entering Timing
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Basic Interval Timer Vector Table Address
Entry Address
General-purpose register save/restore using push and pop instructions;
0FFE6H 0FFE7H
012H 0E3H
0E312H 0E313H
0EH 2EH
main task acceptance of interrupt interrupt service task saving registers
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. restoring registers interrupt return
A maskable interrupt is not accepted until the I-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the I-flag is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which is the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-6 .
Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions
INTxx: PUSH PUSH LDA PUSH A X DPGR A ;SAVE ACC. ;SAVE X REG. ;SAVE DPGR ; Direct page ; accessable reg. ;
=0 B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE
RET
: interrupt processing :
Figure 19-6 Execution of BRK/TCALL0
POP STA POP POP RETI
A DPGR X A
;RESTORE DPGR ;RESTORE X REG. ;RESTORE ACC. ;RETURN
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19.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Main Program service
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER 1 service INT0 service
enable INT0 disable other EI
Occur TIMER1 interrupt
Occur INT0
TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI
A X Y IENH,#80H IENL,#0
;Enable INT0 only ;Disable other ;Enable Interrupt
enable INT0 enable other
IENH,#FFH IENL,#FEH Y X A
;Enable all interrupts
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 19-7 Execution of Multi Interrupt
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19.4 External Interrupt
The external interrupt on INT0, INT1... pins are edge triggered depending the edge selection register. Refer to "6. PORT STRUCTURES" on page 10. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. INT0, INT1 and INT2 are multiplexed with general I/O ports. To use external interrupt pin, the bit of port function register FUNC1 should be set to "1" correspondingly.
Response Time The INT0, INT1 and INT2 edge are latched into INT0IF, INT1IF and INT2IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. For example, the DIV instruction takes twelve machine cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine
INT0 pin
INT0IF INT0 INTERRUPT
edge selection
INT1 pin
INT1IF INT1 INTERRUPT
INT2 pin
INT2IF
INT2 INTERRUPT
IEDS [00F2H]
Figure 19-8 External Interrupt Block Diagram
System clock
Instruction Fetch Last instruction execution (0~12cycle) Interrupt request sampling 1cycle Interrupt overhaed (9~21cycle) Enter interrupt service routine (8cycle)
Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead )
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20. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
6-bit up-counter Clock source (BIT overflow : IFBIT)
WDT
clear comparator IFWDT Watchdog Timer interrupt
6-bit compare data
to reset CPU
enable WDTON[bit5]
6
WDTCL[bit6] WDTR[bit5~0]
WDTR
[00D7 H] Watchdog Timer Register [00D6H]
CKCTLR
Clock control Register
Figure 20-1 Block Diagram of Watchdog Timer
Watchdog Timer Control Figure 20-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary counters unless the binary counter are cleared. At this time, when WDTON=1 a reset is generated, which drives the RESET pin low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (IFWDT) is generated.
CKTCLR ADDRESS : 00D6H RESET VALUE : 0000 0000b
W WDT ON W W W W R ENP BTCL BTS2 BTS1 BTS0 CK
Watchdog timer On/Off control 0: Normal 6bit timer, Watchdog off 1: Watchdog timer ADDRESS : 00D7H RESET VALUE : -011 1111b
W W W W W W ~ W 0
WDTR
WDT CL
W DTR5
Slave address Watchdog timer Clear 0: Watchdog timer free run 1: Watchdog timer clear and free run Automatically cleared this bit after 1cycle
Figure 20-2 Watchdog timer register
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HMS81C43XX / GMS87C4060
Example: Sets the watchdog timer detection time
LDM LDM Within WDT detection time LDM : : : : LDM : : : : LDM WDTR,#01??????b CKCTLR,#00111???b WDTR,#01??????b ;Clear Counter and set value(??????b) ;You have to set WDTR first, for prevent unpredictable interrupt ;when you set WDTON bit. ;Select clock source(???b) and WDTON=1 ;Clear counter
Within WDT detection time
WDTR,#01??????b
;Clear counter
WDTR,#01??????b
;Clear counter
Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON (bit 5 in CKTCLR) to "1". WDTON is initialized to "0" during reset, WDTON should be set to "1" to operate after reset is released. Example: Enables watchdog timer reset
: LDM : : CKTCLR,#001?????b ;WDTON1
Example: 6-bit timer interrupt setting up.
LDX TXSP LDM LDM : : ;SP 3F CKTCLR,#000?????b ;WDTON0 WDTR,#01??????b ;WDTCL0 #03FH
Refer table and see BIT timer ().
CKCTLR BTS2~0 000b 001b BIT input clock PS4 (2uS) PS5 (4uS) PS6 (8uS) PS7 (16uS) PS8 (32uS) PS9 (64uS) PS10 (128uS) PS11 (256uS) Watchdog timer input clock 512uS 1,024uS 2,048uS 4,096uS 8,192uS 16,384uS 32,768uS 65,536uS
The watchdog timer is disabled by clearing bit 5 (WDTON) of CKTCLR.
IFWDT cycle 32,256uS 64,512uS 129,024uS 258,048uS 516,096uS 1,032,192uS 2,064,384uS 4,128,768uS
Watchdog Timer Interrupt The watchdog timer can also be used as a simple 6-bit timer by clearing bit 5 (WDTON) of CKTCLR. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.
010b 011b 100b 101b 110b 111b
= x

The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source.
Table 20-1 Watchdog timer MAX. cycle (Ex:fex =8MHz)
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Source clock BIT overflow
Binary-counter
1
2
3
0
1
2
3
0 Counter Clear
WDTR IFWDT interrupt
n
3 Match Detect
WDTR "0100_0011b" WDT reset reset
Figure 20-3 Watchdog timer Timing
Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. See Figure 20-4 .
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INPUT PIN internal pull-up
VDD
VDD
OUTPUT PIN ON OPEN ON OFF
VDD
O
i GND VDD
OFF
O
i GND ON VDD
X
Weak pull-up current flows
OPEN
X
OFF
O
O
In the left case, much current flows from port to GND.
VDD INPUT PIN OUTPUT PIN VDD i=0 OPEN i L L OFF i GND Very weak current flows ON i=0 GND VDD
O
ON OFF
X
i=0
GND
X
O
O
When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.
In the left case, Tr. base current flows from port to GND. To avoid power consumption, low output to the port .
Figure 20-4 Application example of Port under Power Consumption
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21. OSCILLATOR CIRCUIT
The HMS81C43XX/GMS87C4060 has two oscillation circuits internally. XIN and X OUT are input and output for main frequency and OSC1 and OSC2 are input and output for OSD(On Screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 21-1 .
Recommend C1 XOUT fc (MHz) 4 C2 fc (MHz) 30 XIN VSS 6 8 5 C1 & C2 (pF)
Crystal Oscillator
Recommend C1 OSC2 L1 C2 OSC1 VSS fc (MHz) 8 12 16 20 C1 & C2 (pF) 5 20 10 5 L (uH) 100 15 15 15 For selection L,C value, you have to tune the frequency to appropriate range which is dependent to your target set.
LC Oscillator
Open
XOUT
External Clock
XIN
External Oscillator Figure 21-1 Oscillation Circuit
Oscillation components have their own characteristics, so user should consult the component manufacturers for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XOUT XIN
Figure 21-2 Layout example of Oscillator PCB circuit
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22. RESET
The HMS81C43XX/GMS87C4060 have two types of reset generation procedures; one is an external reset input, other
On-chip Hardware Program counter RAM page register G-flag of PSW PC DPGR G Initial Value (FFFFH) - (FFFEH) 00H 0
is a watch-dog timer reset. Table 22-1 shows on-chip hardware initialization by reset action.
On-chip Hardware Peripheral clock Watchdog timer Control registers Initial Value Off Disable Refer to Table 8-1 on page 22
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connecting for simple power-on-reset is shown in Figure 22-1 .
VDD
RESET + - GND MCU
Figure 22-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
~ ~
Oscillator (XIN pin) RESET Fetch
ADDRESS BUS DATA BUS
?
~ ~ ~ ~
? ? ?
FFFE FFFF Start
~ ~ ~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST = 62.5mS at 4.19MHz
Figure 22-2 Timing Diagram after RESET
~ ~
RESET Process Step 1 fMAIN /1024 MAIN PROGRAM tST = x 256
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22.2 Watchdog Timer Reset
Refer to "20. WATCHDOG TIMER" on page 77.
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23. OTP Programming
23.1 GMS87C4060 OTP Programming
You can burn out GMS87C4060 OTP through the general Gang programmer using Intel 27010/C010 mode. In Devleopment tool package auxiliary, GMS87C4060-to-27010/ C010 conversion socket is included. GMS87C4060 have two ROM memory areas. One is Program ROM memory and the other is Font ROM memory. Program ROM area is from 1000h to FFFFh Font ROM area is from 10000h to 13FFFh. When you acquire new OTP, actually, the OTP is not fully blank. The OPT have six test pattern in the OSD Font ROM memory(see figure23-1). The test pattern are written at 11FA0h ~ 11FFFh and 13FA0h ~ 13FFFh.
Note: DO NOT write any data in this area(11FA0h ~ 11FFFh, 13FA0h ~ 13FFFh)
file(***.OTP) and the other is font OTP file(***.FNT). You can make each file through ASMLINKER.exe and OSDFONT.exe respectively. All OTP file is Motolora Sformat. You can burn the program file and font file respectively or together. To burn program file and font file respectively, refer following procedure 1. Make program OTP file and font OTP file repectively. 2. Check whether six test pattern is included in font OTP file(see below Six Text Pattern) 3. Burn program OTP file(Set chip target address 1000h ~ FFFFh) 4. Burn font OTP file(Set chip target address 10000h ~13FFFh)
Note: When you program the OTP file, DO NOT check the blank. Because there are already written data(Six test pattern / 11FA0h ~ 11FFFh, 13FA0h~13FFFh) It will occur blank error
Blank Check If you run blank check function of ROM writer, ROM writer inform blank error because of test pattern. To avoid this situation, you must run the blank check function seperetely. For example, check OTP address rage of 1000h ~ 11F9Fh at first. And then check OPT address range of 12000h ~ 13F9Fh. If you have ROM writer without partial blank check function, please do not run blank check function.
1000H
To burn program file and font file together, refer following procedure 1. Add program OTP file and font OTP file 2. Check whether six test pattern is included in font OTP file(see below Six Text Pattern)
Program Memory
3. Burn OTP file(Set chip target address 1000h ~ 13FFFh) About other details, refer ROM wirter manual. Six Test Pattern
FFFFH OSD Font Memory 13FFFH
When you make font file through OSDFONT.exe, please confirm whether six test pattern is included or not in character address 1FAh ~ 1FFh, To include six test patern, refer following procedure. 1. Make Font file and save it to your PC
Figure 23-1 GMS87C4060 OTP Memory Map
2. Reopen the font file and save it to your HDD once again. 3. Then six test pattern will be included automatically. (Character address 1FAh ~ 1FFh)
Program Writing There are two kind of OTP file. One is program OTP
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23.2 .Device configuration data
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 GND
A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 A16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
CEB
Figure 23-2 Figure Pin Configuration in OTP Programming Mode
HYNIX GMS87C4060
PGMB OEB VCC VPP
O0 O1 O2
GMS87C4060 Mode Program Verify Optional Verify Gang Write *3 Gang Verify *4 VPP 12.75V 12.75V 5V 12.75V 12.75V, 5V CEB Low Low Low Low Low OEB High*2 Low Low High Low PGMB Low*1 High X Low X VPP 12.75V 12.75V 5V 12.75V 12.75V
Intel 27010 CEB Low Low Low Low Low OEB High Low Low High Low PGMB Low High X Low X
Figure 23-3 Figure Mode Table
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*1: Low = Input Low Voltage = VIL(<0.8V) *2: High = Input High Value = VIL(>2.0V) *3: In Gang Write Mode, All OTPs are programmed simulaneously. So all signals of OTPs are in the same condition
*4: In Gang Verify mode, the VPP pin can be sset to both normal high(5V), aand 12.75V and chip slecection is possible using the CEB pin
SYMBOL tAS tOES tDS tAH tDH tDFP tVPS tCES tPW tOE tACC tOH
Parameter Address Setup Time OEB Setup Time Data Setup Time Address Hold Time Data Hold Time OEB High to Output Float Delay Vpp Setup Time CEB Setup Time PGMB initial program pulse width Min 2 2 2 0 2 0 2 2 95
Limits Typ Max
Conditions Unit s s s s s ns s s s ns ns ns ns ns
130
Note1
100
105
Quick pulse programming
Data Valid from OEB 100 Address to output delay 150 output hold from addresses CEB or 0 0 OEB whichever occurrs first tCE CEB to output delay 100 tCS chip selection interval 100 (@Gang verify) *Note1: Output Float is defined as the point where data is no longer driven
Figure 23-4 Figure AC Programming Characteristics
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Intel 27010 Pin Name VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND O3 O4 O5 O6 O7 CEB A10 OEB A11 A9 A8 A13 A14 N.C. PGMB VCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name TEST_N R67 R27 R24 R17 R16 R15 R14 R13 R12 R11 R10 R00 R01 R02 VSS R03 R04 R05 R06 R07 R41 R22 R53 R23 R21 R20 R25 R26 R52 VDD
GMS87C4060 Pin Number 38 26 1 4 9 10 15 16 17 18 19 20 29 28 27 12, 40 25 24 23 22 21 51 6 41 5 7 8 3 2 42 39
Figure 23-5 Pin Mapping Table between Intel 27010/C010 and GMS87C4060
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HMS81C43XX / GMS87C4060
Pin Name RESET_N Xout Xin R G B R56 R55 R54 OSC2 OSC1 R47 R46 R45 R44 R43 R42 R40 R50 R51
Pin Number 11 13 14 30 31 32 33 34 35 36 37 45 46 47 48 49 50 52 44 43
Connect to GND Not Connect GND Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect GND GND GND GND GND Not Connect Not Connect GND VDD VDD
Figure 23-6 Connection of Other Pins of GMS87C4060 in OTP Mode
23.3 Timing Chart
Program
Verify
Optinal Verify Address Valid tAH
Address
VIH Address Stable VIL tAS High Z
VIH
Data
Data in Stable VIL tDS tDH
Data out Valid tDFP
Valid ouput
12.5V
VPP
tVPS 5V
VIH
CEB
Don't care tCES
Don't care
VIL
PGMB
VIH VIL VIH VIL tOES tPW tOE
Don't care tOE
OEB
Figure 23-7 Figure Programming Timing Chart
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Optinal Verify
Address
VIH Address Stable VIL VIH Data VIL VIH 0th OTP Data 1st OTP
Data
.....
Data (n-1)th OTP
OEB
VIL VIH VIL
tACC
CEB[0]
tCS tACC
CEB[1]
VIH VIL tACC VIH VIL
CEB[n-1]
1) When you verify the data in the same address of many OTPs.
When you select OTPs using CEB, and can verify the data inthe same address. (PGMB : Don't care , Vpp : VIH or 12.5V )
VIH
OEB
VIL VIH VIL
tACC
CEB[0]
tCS tACC
CEB[1]
VIH VIL tACC
CEB[n-1]
VIH VIL VIH
OEB
VIL VIH VIL VIH Addr0 VIL tACC VIH Data0 VIL Data1 Data2 Addr1 tACC Addr2 tACC Addr3 tACC Data3 tACC
CEB[0]
Address
Data
2) When you verify the data in s single OTP throughout the ROM address Figure 23-8 AC Wave Form in Gang Verify Mode
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24. Assemble mnemonics
24.1 Instruction Map
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
000 001 010
NOP CLRC CLRG
SET1
dp.bit
BBS
A.bit,rel
BBS
dp.bit,rel
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
TCALL SETA1
0 .bit
BIT
dp
POP
A
PUSH
A
BRK BRA
rel
//
//
//
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1 COM
2 .bit dp
POP
X
PUSH
X
//
//
//
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL NOT1
4 M.bit
TST
dp
POP
Y
PUSH PCALL
Y Upage
011
DI
//
//
//
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1 OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET INC
X
100
CLRV
//
//
//
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1 CMPY CBNE 8 dp dp+X AND1B TCALL EOR1 DBNE 10 dp EOR1B TCALL
12
TXSP
101
SETC
//
//
//
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
//
//
//
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
LDC LDCB STC
M.bit
LDX
dp
LDX
dp+Y
XCN
DAS
111
EI
//
//
//
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STX
dp
STX
dp+Y
XAS
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
000 001 010 011 100 101 110 111
BPL
rel
CLR1
dp.bit
BBC
A.bit,rel
BBC
dp.bit,rel
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
BVC
rel
//
//
//
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL CALL
3 !abs
TEST SUBW
!abs dp
LDY
#imm
JMP
[dp]
BCC
rel
//
//
//
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
TCLR1 CMPW CMPX
!abs dp #imm
CALL
[dp]
BNE
rel
//
//
//
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL DBNE CMPX LDYA CMPY
7 Y !abs dp #imm
RETI TAY TYA DAA NOP
BMI
rel
//
//
//
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV XMA
{X}
CMPY INCW
!abs dp
INC
Y
BVS
rel
//
//
//
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
dp
DECW
dp
DEC
Y
BCS
rel
//
//
//
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY XYX
BEQ
rel
//
//
//
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
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24.2 Alphabetic order table of instruction
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} ADDW dp AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} AND1 M.bit AND1B M.bit ASL A ASL dp ASL dp + X ASL !abs BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BIT dp BIT !abs BMI rel BNE rel BPL rel BRA rel BRK OP CODE 04 05 06 07 15 16 17 14 1D 84 85 86 87 95 96 97 94 8B 8B 08 09 19 18 y2 y3 x2 x3 50 D0 F0 0C 1C 90 70 10 2F 0F BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 2 3 3 2 2 1 3 3 1 2 2 3 2 3 2 3 2 2 2 2 3 2 2 2 2 1 CYCLE NO 2 3 4 4 5 6 6 3 5 2 3 4 4 5 6 6 3 4 4 2 4 5 5 4/6 5/7 4/6 5/7 2/4 2/4 2/4 4 5 2/4 2/4 2/4 4 8 Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Arithmetic shift left -------C -------C N-----Z16-bits add without carry : YA YA + (dp+1)(dp) Logical AND A A ^ (M) NV - - H - ZC NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Bit test A with memory : Z A ^ M, N (M7), V (M6) Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PC L), SP S - 1, M(SP) PSW, SP SP - 1, PC L (0FFDEH), PC H (0FFDFH)
--------------MM - - - - Z --------------MM - - - - Z -----------------------------
---1-0--
38 39 40 41 42 43 44 45 46 47
BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel CLR1 dp.bit CLR1A A.bit CLRC CLRG
30 B0 3B 5F FD 8D y1 2B 20 40
2 2 3 2 3 3 2 2 1 1
2/4 2/4 8 8 5/7 6/8 4 2 2 2
Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel Subroutine call M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0"
---------------
--------
----------------------------0 --0-----
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NO. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
MNENONIC CLRV CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPW dp CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DBNE dp,rel DBNE Y,rel DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DECW dp DI DIV EI EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} EOR1 M.bit EOR1B M.bit INC A INC dp INC dp + X INC !abs INC X INC Y INCW dp JMP !abs JMP [!abs] JMP [dp]
OP CODE 80 44 45 46 47 55 56 57 54 5D 5E 6C 7C 7E 8C 9C 2C DF CF AC 7B A8 A9 B9 B8 AF BE BD 60 9B E0 A4 A5 A6 A7 B5 96 97 94 AB AB 88 89 99 98 8F 9E 9D 1B 1F 3F
BYTE NO. 1 2 2 2 3 3 2 2 1 2 2 2 3 2 2 3 2 1 1 3 2 1 2 2 3 1 1 2 1 1 1 2 2 2 3 3 2 2 1 3 3 1 2 2 3 1 1 2 3 3 2
CYCLE NO 2 2 3 4 4 5 6 6 3 4 2 3 4 2 3 4 4 3 3 5/7 4/6 2 4 5 5 2 2 6 3 12 3 2 3 4 4 5 6 6 3 5 5 2 4 5 5 2 2 6 3 5 4 Clear V-flag : V "0"
OPERATION
FLAG NVGBHIZC -0--0---
Compare accumulator contents with memory contents A - (M)
N - - - - - ZC
Compare YA contents with memory pair contents : YA - (dp+1)(dp) Compare X contents with memory contents X - (M) Compare Y contents with memory contents Y - (M) 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement and branch if not equal : if (M) 0, then PC PC + rel. Decrement MM-1
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC N-----ZN - - - - - ZC N - - - - - ZC --------
N-----Z-
Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Disable interrupts : I "0" Divide : YA / X Q:A, R:Y Enable interrupts : I "1" Exclusive OR A A (M)
N-----Z-----0-NV - - H - Z -----1--
N-----Z-
Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Increment (M) (M) + 1
-------C -------C N - - - - - ZC
N-----Z-
Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 Unconditional jump PC jump address
N-----Z--------
92
N ov e m b er 2 0 0 1 v e r 1 .2
HMS81C43XX / GMS87C4060
NO. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
MNENONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDC M.bit LDCB M.bit LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs LDYA dp LSR A LSR dp LSR dp + X LSR !abs MUL NOP NOT1 M.bit OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} OR1 M.bit OR1B M.bit PCALL
OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB CB CB E4 1E CC CD DC 3E C9 D9 D8 7D 48 49 59 58 5B 00,FF 4B 64 65 66 67 75 76 77 74 6B 6B 4F
BYTE NO. 2 2 2 3 3 2 2 1 1 3 3 3 2 2 2 3 2 2 2 3 2 1 2 2 3 1 1 3 2 2 2 3 3 2 2 1 3 3 2
CYCLE NO 2 3 4 4 5 6 6 3 4 4 4 5 2 3 4 4 2 3 4 4 5 2 4 5 5 9 2 5 2 3 4 4 5 6 6 3 5 5 6 Load X-register Y (M) Load accumulator A (M)
OPERATION
FLAG NVGBHIZC
N-----Z-
X-register auto-increment : A (M), X X + 1 Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------C -------C --------
N-----Z-
Load YA : YA (dp+1)(dp) Logical shift right
N-----Z-
76543210 C "0"
Multiply : YA Y x A No operation Bit complement : (M.bit) ~(M.bit) Logical OR A A V (M)
N - - - - - ZC
N-----Z---------------
N-----Z-
Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PC L (upage), PCH "OFFH"
-------C -------C --------
138 139 140 141 142 143 144 145 146 147
POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI
0D 2D 4D 6D 0E 2E 4E 6E 6F 7F
1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 5 6
Pop from stack SP SP + 1, Reg. M(SP) -------(restored) Push to stack M(SP) Reg. SP SP - 1 --------
Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP)
--------
(restored)
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NO. 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187
MNENONIC ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X} SET1 dp.bit SETA1 A.bit SETC SETG STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STC M.bit STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs STYA dp SUBW dp TAX TAY TCALL n
OP CODE 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 x1 0B A0 C0 E5 E6 E7 F5 F6 F7 F4 FB EB EC ED FC E9 F9 F8 DD 3D E8 9F nA
BYTE NO. 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 2 1 1 2 2 3 3 2 2 1 1 3 2 2 3 2 2 3 2 2 1 1 1
CYCLE NO 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 4 2 2 2 3 4 4 5 6 6 3 4 6 4 5 5 4 5 5 5 5 2 2 8
OPERATION Rotate left through carry
FLAG NVGBHIZC
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store accumulator contents in memory (M) A
---------------------1 --1-----
--------
X-register auto-increment : (M) A, X X + 1 Store C-flag : (M.bit) C Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp) Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PC L (Table vector L), PCH (Table vector H) ---------------------NV - - H - ZC N-----ZN-----Z---------------
188 189 190 191 192 193 194 195 196
TCLR1 !abs TSET1 !abs TSPX TST dp TXA TXSP TYA XAX XAY
5C 3C AE 4C C8 8E BF EE DE
3 3 1 2 1 1 1 1 1
6 6 2 3 2 2 2 4 4
Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) Transfer stack-pointer contents to X-register : X SP Test memory contents for negative or zero : (dp) - 00H Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA
N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z---------------
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N ov e m b er 2 0 0 1 v e r 1 .2
HMS81C43XX / GMS87C4060
NO. 197 198 199 200 201
MNENONIC XCN XMA dp XMA dp + X XMA {X} XYX
OP CODE CE BC AD BB FE
BYTE NO. 1 2 2 1 1
CYCLE NO 5 5 6 5 4 A7 ~ A4 f A3 ~ A0
OPERATION Exchange nibbles within the accumulator: Exchange memory contents with accumulator (M) f A Exchange X-register contents with Y-register : X f Y
FLAG NVGBHIZC N-----Z-
N-----Z--------
24.3 Instruction Table by Function 1. Arithmetic/Logic Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y OP CODE 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1 CYCLE NO 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement MM-1 N-----ZN-----ZN - - - - - ZC N - - - - - ZC Compare Y contents with memory contents Y - (M) N - - - - - ZC Compare X contents with memory contents X - (M) N - - - - - ZC N - - - - - ZC Arithmetic shift left N-----ZLogical AND A A ^ (M) NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Compare accumulator contents with memory contents A - (M)
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HMS81C43XX / GMS87C4060
NO. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV
MNENONIC
OP CODE 9B A4 A5 A6 A7 B5 96 97 94 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
BYTE NO. 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
CYCLE NO 12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Logical shift right Increment (M) (M) + 1 Exclusive OR A A (M)
OPERATION Divide : YA / X Q:A, R:Y
FLAG NVGBHIZC NV - - H - Z -
EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X} TST dp XCN
N-----Z-
N - - - - - ZC
N-----Z-
76543210 C "0"
Multiply : YA Y x A Logical OR A A V (M)
N - - - - - ZC
N-----Z-
N-----Z-
Rotate left through carry
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
Test memory contents for negative or zero : (dp) - 00H Exchange nibbles within the accumulator: A7 ~ A4 f A3 ~ A0
N-----ZN-----Z-
96
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HMS81C43XX / GMS87C4060
2. Register / Memory Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNENONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp + X XMA {X} XYX OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE BYTE NO. 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 CYCLE NO 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 3 4 4 5 6 6 3 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Exchange X-register contents with Y-register : X f Y -------Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X SP Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA Exchange memory contents with accumulator (M) f A N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------Store Y-register contents in memory (M) Y -------X-register auto-increment : (M) A, X X + 1 Store X-register contents in memory (M) X --------------Store accumulator contents in memory (M) A Load X-register Y (M) N-----ZX-register auto-increment : A (M), X X + 1 Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------N-----ZLoad accumulator A (M) OPERATION FLAG NVGBHIZC
3. 16-Bit Operation
NO. 1 2 3 4 MNENONIC ADDW dp CMPW dp DECW dp INCW dp OP CODE 1D 5D BD 9D BYTE NO. 2 2 2 2 CYCLE NO 5 4 6 6 OPERATION 16-bits add without carry : YA YA + (dp+1)(dp) Compare YA contents with memory pair contents : YA - (dp+1)(dp) Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 N-----ZN-----ZFLAG NVGBHIZC NV - - H - ZC N - - - - - ZC
November 2001 ver 1.2
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HMS81C43XX / GMS87C4060
NO. 5 6 7
MNENONIC LDYA dp STYA dp SUBW dp
OP CODE 7D DD 3D
BYTE NO. 2 2 2
CYCLE NO 5 5 5
OPERATION Load YA : YA (dp+1)(dp) Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp)
FLAG NVGBHIZC N-----Z-------NV - - H - ZC
4. Bit Manipulation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNENONIC AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLR1A A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs OP CODE 8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C BYTE NO. 3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 CYCLE NO 4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 OPERATION Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Bit test A with memory : Z A ^ M, N (M7), V (M6) Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Bit complement : (M.bit) ~(M.bit) Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : (M.bit) C Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) FLAG NVGBHIZC -------C -------C MM - - - - Z ---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
5. Branch / Jump Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 MNENONIC BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel OP CODE y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 BYTE NO. 2 3 2 3 2 2 2 2 2 2 2 2 2 CYCLE NO 4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel OPERATION FLAG NVGBHIZC --------------MM - - - - Z ---------------------------------------------------------
98
N ov e m b er 2 0 0 1 v e r 1 .2
HMS81C43XX / GMS87C4060
NO. 14 15 16 17 18 19 20 21 22 23
MNENONIC CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL
OP CODE 3B 5F FD 8D AC 7B 1B 1F 3F 4F
BYTE NO. 3 2 3 3 3 2 3 3 2 2
CYCLE NO 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Subroutine call
OPERATION
FLAG NVGBHIZC --------
M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Decrement and branch if not equal : if (M) 0, then PC PC + rel. Unconditional jump PC jump address U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PC L (upage), PCH "OFFH"
---------------
--------
--------
24
TCALL n
nA
1
8
Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PC L (Table vector L), PCH (Table vector H) --------
6. Control Operation & etc.
NO. 1 MNENONIC BRK OP CODE 0F BYTE NO. 1 CYCLE NO 8 Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PC L), SP S - 1, M(SP) PSW, SP SP - 1, PC L (0FFDEH), PC H (0FFDFH) 2 3 4 5 6 7 8 9 10 11 12 13 14 DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F 7F 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 2 4 4 4 4 4 4 4 4 5 6 Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP) (restored) -------Push to stack M(SP) Reg. SP SP - 1 -------(restored) Disable interrupts : I "0" Enable interrupts : I "1" No operation Pop from stack SP SP + 1, Reg. M(SP) ------------0------1-----------1-0-OPERATION FLAG NVGBHIZC
November 2001 ver 1.2
99
HMS81C43XX / GMS87C4060
100
N ov e m b er 2 0 0 1 v e r 1 .2

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